A Self-Supervised, Pre-Trained, and Cross-Stage-Aligned Circuit Encoder Provides a Foundation for Various Design Tasks

Conference paper

AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs

Conference paper

FirePower: Towards a Foundation with Generalizable Knowledge for Architecture-Level Power Modeling

Conference paper

Integrating Prefetcher Selection with Dynamic Request Allocation Improves Prefetching Efficiency

Conference paper

Pointer: An Energy-Efficient ReRAM-based Point Cloud Recognition Accelerator with Inter-layer and Intra-layer Optimizations

Conference paper

PRICING: Privacy-Preserving Circuit Data Sharing Framework for Lithographic Hotspot Detection

Conference paper

SMART-GPO: Gate-Level Sensitivity Measurement with Accurate Estimation for Glitch Power Optimization

Conference paper

Towards Big Data in AI for EDA Research: Generation of New Pseudo-Circuits at RTL Stage

Conference paper

An Architecture-Level CPU Modeling Framework for Power and Other Design Qualities

Article

Data-Pattern-Based Predictive On-Chip Power Meter in DNN Accelerator

Article

FADO: Floorplan-Aware Directive Optimization Based on Synthesis and Analytical Models for High-Level Synthesis Designs on Multi-Die FPGAs

Article

Large circuit models: opportunities and challenges

Article

RTLCoder: Fully Open-Source and Efficient LLM-Assisted RTL Code Generation Technique

Article

Towards Fully Automated Machine Learning for Routability Estimator Development

Article

Transferable Pre-Synthesis PPA Estimation for RTL Designs With Data Augmentation Techniques

Article

Accel-NASBench: Sustainable Benchmarking for Accelerator-Aware NAS

Conference paper

Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization

Conference paper

APPLE: An Explainer of ML Predictions on Circuit Layout at the Circuit-Element Level

Conference paper

EDALearn: A Comprehensive RTL-to-Signoff EDA Benchmark for Democratized and Reproducible ML for EDA Research

Conference paper

OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation

Conference paper

RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model

Conference paper

Unleashing Flexibility of ML-based Power Estimators Through Efficient Development Strategies

Conference paper

The Dark Side: Security and Reliability Concerns in Machine Learning for EDA

Article

Deep Learning for Routability

Book chapter

Net-Based Machine Learning-Aided Approaches for Timing and Crosstalk Estimation

Book chapter

Efficient Runtime Power Modeling with On-Chip Power Meters

Conference paper

FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAs

Conference paper

Fully Automated Machine Learning Model Development for Analog Placement Quality Prediction

Conference paper

MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design

Conference paper

PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions

Conference paper

PertNAS: Architectural Perturbations for Memory-Efficient Neural Architecture Search

Conference paper

PROPHET: Predictive On-Chip Power Meter in Hardware Accelerator for DNN

Conference paper

Rethink before Releasing Your Model: ML Model Extraction Attack in EDA

Conference paper

Security and Reliability Challenges in Machine Learning for EDA: Latest Advances

Conference paper

Pre-Placement Net Length and Timing Estimation by Customized Graph Neural Network

Article

DEEP: Developing Extremely Efficient Runtime On-Chip Power Meters

Conference paper

Robustify ML-based Lithography Hotspot Detectors

Conference paper

Towards Collaborative Intelligence: Routability Estimation based on Decentralized Private Data

Conference paper

APOLLO: An automated power modeling framework for runtime power introspection in high-volume commercial microprocessors

Conference paper

Automatic Routability Predictor Development Using Neural Architecture Search

Conference paper

Net2: A Graph Attention Network Method Customized for Pre-Placement Net Length Estimation

Conference paper

Fast IR Drop Estimation with Machine Learning : Invited Paper

Conference paper

FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning

Conference paper

PowerNet: Transferable Dynamic IR Drop Estimation via Maximum Convolutional Neural Network

Conference paper

Routing-Free Crosstalk Prediction

Conference paper

Routability-Driven Macro Placement with Embedded CNN-Based Prediction Model

Conference paper

RouteNet: Routability prediction for mixed-size designs using convolutional neural network

Conference paper