Large-scale self-normalizing neural networks

NoCFuzzer: Automating NoC Verification in UVM

Survey of Machine Learning for Software-assisted Hardware Design Verification: Past, Present, and Prospect

A Comprehensive Survey on Distributed Training of Graph Neural Networks

Comprehensive SNN Compression Using ADMM Optimization and Activity Regularization

Exploring Adversarial Attack in Spiking Neural Networks With Spike-Compatible Gradient

ReDCIM: Reconfigurable Digital Computing-in-Memory Processor with Unified FP/INT Pipeline for Cloud AI Acceleration

SDP: Co-Designing Algorithm, Dataflow, and Architecture for In-SRAM Sparse NN Acceleration

SPCIM: Sparsity-Balanced Practical CIM Accelerator with Optimized Spatial-Temporal Multi-Macro Utilization

TranCIM: Full-Digital Bitline-Transpose CIM-based Sparse Transformer Accelerator With Pipeline/Parallel Reconfigurable Modes

ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis

DF-GAS: a Distributed FPGA-as-a-Service Architecture towards Billion-Scale Graph-based Approximate Nearest Neighbor Search

Klotski: DNN Model Orchestration Framework for Dataflow Architecture Accelerators

RM-STC: Row-Merge Dataflow Inspired GPU Sparse Tensor Core for Energy-Efficient Sparse Acceleration

SPG: Structure-Private Graph Database via SqueezePIR

A Comprehensive and Modularized Statistical Framework for Gradient Norm Equality in Deep Neural Networks

A Survey of Machine Learning for Computer Architecture and Systems

A Systematic View of Model Leakage Risks in Deep Neural Network Systems

Accelerating CPU-Based Sparse General Matrix Multiplication with Binary Row Merging

Characterizing and Understanding HGNNs on GPUs

Dynamic Sparse Attention for Scalable Transformer Acceleration

EPQuant: A Graph Neural Network compression approach based on product quantization

H2Learn: High-Efficiency Learning Accelerator for High-Accuracy Spiking Neural Networks

Hardware-Enabled Efficient Data Processing with Tensor-Train Decomposition

MPU-Sim: A Simulator for In-DRAM Near-Bank Processing Architectures

OpSparse: a Highly Optimized Framework for Sparse General Matrix Multiplication on GPUs

Practical Near-Data-Processing Architecture for Large-Scale Distributed Graph Neural Network

Rubik: A Hierarchical Architecture for Efficient Graph Neural Network Training

SaARSP: An Architecture for Systolic-Array Acceleration of Recurrent Spiking Neural Networks

STPAcc: Structural TI-Based Pruning for Accelerating Distance-Related Algorithms on CPU-FPGA Platforms

Towards Efficient Superconducting Quantum Processor Architecture Design

184QPS/W 64Mb/mm²3D Logic-to-DRAM Hybrid Bonding with Process-Near-Memory Engine for Recommendation System

A 28nm 15.59J/Token Full-Digital Bitline-Transpose CIM-Based Sparse Transformer Accelerator with Pipeline/Parallel Reconfigurable Modes

A 28nm 29.2TFLOPS/W BF16 and 36.5TOPS/W INT8 Reconfigurable Digital CIM Processor with Unified FP/INT Pipeline and Bitwise In-Memory Booth Multiplication for Cloud Deep Learning Acceleration

A one-for-all and o(v log(v ))-cost solution for parallel merge style operations on sorted key-value arrays

A Synthesis Framework for Stitching Surface Code with Superconducting Qantum Devices

Accelerating Spatiotemporal Supervised Training of Large-Scale Spiking Neural Networks on GPU

AI-assisted Synthesis in Next Generation EDA: Promises, Challenges, and Prospects

Alleviating datapath conflicts and design centralization in graph analytics acceleration

BEACON: Scalable Near-Data-Processing Accelerators for Genome Analysis near Memory Pool with the CXL Support

COMB-MCM: Computing-on-Memory-Boundary NN Processor with Bipolar Bitwise Sparsity Optimization for Scalable Multi-Chiplet-Module Edge Machine Learning

DIMMining: Pruning-Efficient and Parallel Graph Mining on Near-Memory-Computing

DOTA: Detect and OmitWeak Attentions for Scalable Transformer Acceleration

Effective Model Sparsi cation by Scheduled Grow-and-Prune Methods

Heuristic adaptability to input dynamics for SpMM on CPUs

High-Level Synthesis Performance Prediction using GNNs: Benchmarking, Modeling, and Advancing

Hyperscale FPGA-as-a-Service Architecture for Large-Scale Distributed Graph Neural Network

INSPIRE: IN-Storage Private Information REtrieval via Protocol and Architecture Co-design

Paulihedral: A generalized block-wise compiler optimization framework for quantum simulation kernels

Shfl-BW: Accelerating Deep Neural Network Inference with Tensor-Core AwareWeight Pruning

Toward Robust Spiking Neural Network Against Adversarial Perturbation

Understanding GNN Computational Graph: A Coordinated Computation, IO, and Memory Perspective

DLUX: A LUT-Based Near-Bank Accelerator for Data Center Deep Learning Training Workloads

Effective and Efficient Batch Normalization Using a Few Uncorrelated Data for Statistics Estimation

Evolver: A Deep Learning Processor with On-Device Quantization-Voltage-Frequency Tuning

Fast search of the optimal contraction sequence in tensor networks

Hardware Acceleration for GCNs via Bidirectional Fusion

Practical Attacks on Deep Neural Networks by Memory Trojaning

Rescuing RRAM-Based Computing from Static and Dynamic Faults

Tensor train decomposition for solving large-scale linear equations

Training and inference for integer-based semantic segmentation network

Π-RT: A Runtime Framework to Enable Energy-Efficient Real-Time Robotic Vision Applications on Heterogeneous Architectures

Brain-Inspired Computing: Adventure from Beyond CMOS Technologies to Beyond von Neumann Architectures

Efficient tensor core-based gpu kernels for structured sparsity under reduced precision

EGEMM-TC: Accelerating scientific computing on tensor cores with extended precision

ENMC: Extreme near-memory classification via approximate screening

GNNAdvisor: An adaptive and efficient runtime system for GNN acceleration on GPUs

Improving streaming graph processing performance using input knowledge

IronMan: GNN-assisted Design Space Exploration in High-Level Synthesis via Reinforcement Learning

NeuroMeter: An Integrated Power, Area, and Timing Modeling Framework for Machine Learning Accelerators Industry Track Paper

On the Co-Design of Quantum Software and Hardware

Overcoming the Memory Hierarchy Inefficiencies in Graph Processing Applications

Palleon: A runtime system for efficient video processing toward dynamic class skew

SEALing Neural Network Models in Encrypted Deep Learning Accelerators

SpaceA: Sparse Matrix Vector Multiplication on Processing-in-Memory Accelerator

A Survey of Accelerator Architectures for Deep Neural Networks

Characterizing and Understanding GCNs on GPU

Comparing SNNs and RNNs on neuromorphic vision datasets: Similarities and differences

Core Placement Optimization for Multi-chip Many-core Neural Network Systems with Reinforcement Learning

Crane: Mitigating accelerator under-utilization caused by sparsity irregularities in cnns

Model Compression and Hardware Acceleration for Neural Networks: A Comprehensive Survey

NMTSim: Transaction-Command Based Simulator for New Memory Technology Devices

NNBench-X: A Benchmarking Methodology for Neural Network Accelerator Designs

Power-efficient neural network with artificial dendrites

Projection-based runtime assertions for testing and debugging Quantum programs

Rethinking the performance comparison between SNNS and ANNS

SemiMap: A Semi-Folded Convolution Mapping for Speed-Overhead Balance on Crossbars

Tianjic: A unified and scalable chip bridging spike-based and continuous neural computation

Training high-performance and large-scale deep neural networks with full 8-bit integers

Nonvolatile Processor Architecture Exploration for Energy-Harvesting Application Scenarios

Boosting Deep Neural Network Effciency with Dual-Module Inference

DeepSniffer: A DNN Model Extraction Framework Based on Learning Architectural Hints

DUET: Boosting deep neural network efficiency on dual-module architecture

EFLOPS: Algorithm and system co-design for a high performance distributed training platform

Eliminating redundant computation in noisy quantum computing simulation

Fulcrum: A simplified control and access mechanism toward flexible and practical in-situ accelerators

fuseGNN: Accelerating Graph Convolutional Neural Network Training on GPGPU

HyGCN: A GCN accelerator with hybrid architecture

IPIM: Programmable In-Memory Image Processing Accelerator Using Near-Bank Architecture

NEST: DIMM based Near-Data-Processing Accelerator for K-mer Counting

SAGA-Bench: Software and Hardware Characterization of Streaming Graph Analytics Workloads

SmartExchange: Trading Higher-cost Memory Storage/Access for Lower-cost Computation

Taming unstructured sparsity on GPUs via latency-aware optimization

Timely: Pushing Data Movements and Interfaces in Pim Accelerators towards Local and in Time Domain

Towards Efficient Superconducting Quantum Processor Architecture Design

Xuantie-910: A Commercial Multi-Core 12-Stage Pipeline Out-of-Order 64-bit High Performance RISC-V Processor with Vector Extension

An instruction set architecture for machine learning

DASM: Data-Streaming-Based Computing in Nonvolatile Memory Architecture for Embedded System

GraphH: A Processing-in-Memory Architecture for Large-Scale Graph Processing

L1 -Norm Batch Normalization for Efficient Training of Deep Neural Networks

Network-on-Chip Design Guidelines for Monolithic 3-D Integration

NNBench-X: Benchmarking and understanding neural network workloads for accelerator designs

Parana: A Parallel Neural Architecture Considering Thermal Problem of 3D Stacked Memory

Power Profiling of Modern Die-Stacked Memory

PXNOR-BNN: In/With Spin-Orbit Torque MRAM Preset-XNOR Operation-Based Binary Neural Networks

TIME: A training-in-memory architecture for RRAM-based deep neural networks

Towards a polynomial algorithm for optimal contraction sequence of tensor networks from trees

Towards artificial general intelligence with hybrid Tianjic chip architecture

低功耗神经网络计算芯片技术研究

Alleviating irregularity in graph analytics acceleration: A hardware/software co-design approach

Analysis and optimization of the memory hierarchy for graph processing workloads

Balancing Memory Accesses for Energy-Efficient Graph Analytics Accelerators

CNNWire: Boosting convolutional neural network with winograd on ReRAM based accelerators

CORN: In-Buffer Computing for Binary Neural Network

Cost-efficient 3D integration to Hinder Reverse Engineering during and after manufacturing

Direct training for spiking neural networks: Faster, larger, better

Efficient system architecture in the era of monolithic 3D: Dynamic inter-tier interconnect and processing-in-memory

FPSA: A Full System Stack Solution for Reconfigurable ReRAM-based NN Accelerator Architecture

Investigation of cost-optimal network-on-chip for passive and active interposer systems

Learning the sparsity for RERAM: Mapping and pruning sparse neural network for ReRAM based accelerator

MEDAL: Scalable DIMM based near data processing accelerator for DNA seeding algorithm

Memory Trojan Attack on Neural Network Accelerators

Memory-bound proof-of-work acceleration for blockchain applications

Near-Data Acceleration of Privacy-Preserving Biomarker Search with 3D-Stacked Memory

Ouroboros: An Inference Engine for Deep Learning Based TTS on Embedded Devices

Sparse tensor core: Algorithm and hardware co-design for vector-wise sparse neural networks on modern GPUs

SuperMem: Enabling application-transparent secure persistent memory with low overheads

Tackling the Qubit Mapping Problem for NISQ-Era Quantum Devices

An Adaptive 3T-3MTJ Memory Cell Design for STT-MRAM-Based LLCs

Crossbar-aware neural network pruning

Die Stacking Is Happening

Exploring Core and Cache Hierarchy Bottlenecks in Graph Processing Workloads

IAA: Incidental Approximate Architectures for Extremely Energy-Constrained Energy Harvesting Scenarios using IoT Nonvolatile Processors

Memory that never forgets: Emerging nonvolatile memory and the implication for architecture design

Mitigating BTI-induced degradation in STT-MRAM sensing schemes

MNSIM: Simulation Platform for Memristor-Based Neuromorphic Computing System

Performance evaluation and optimization of HBM-Enabled GPU for data-intensive applications

Securing Emerging Nonvolatile Main Memory with Fast and Energy-Efficient AES In-Memory Implementation

Stuck-at Fault Tolerance in RRAM Computing Systems

AIM: Fast and energy-efficient AES in-memory implementation for emerging non-volatile main memory

Bridging the gap between neural networks and neuromorphic hardware with a neural network compiler

NEOFog: Nonvolatility-exploiting optimizations for fog computing

Packet pump: Overcoming network bottleneck in on-chip interconnects for GPGPUs

Persistence parallelism optimization: A holistic approach from Memory Bus to RDMA Network

RADAR: A 3D-ReRAM based DNA alignment accelerator architecture

SCOPE: A stochastic computing engine for DRAM-based in-situ accelerator

SNrram: An efficient sparse neural network computation architecture based on resistive random-access memory

A Study on Practically Unlimited Endurance of STT-MRAM

DLAU: A scalable deep learning accelerator unit on FPGA

Dynamic power and energy management for energy harvesting nonvolatile processor systems

Overview of 3-D Architecture Design Opportunities and Techniques

Software-Hardware Codesign for Efficient Neural Network Acceleration

Thermomechanical Stress-Aware Management for 3-D IC Designs

NoC-aware computational sprinting

A 462GOPs/J RRAM-based nonvolatile intelligent processor for energy harvesting IoE system featuring nonvolatile logics and processing-in-memory

Building energy-efficient multi-level cell STT-RAM caches with data compression

Computation-oriented fault-tolerance schemes for RRAM computing systems

Cost-effective design of scalable high-performance systems using active and passive interposers

DRISA: A DRAM-based reconfigurable in-situ accelerator

Incidental computing on IoT nonvolatile processors

Performance evaluation and optimization of HBM-Enabled GPU for data-intensive applications

Security threats and countermeasures in three-dimensional integrated circuits

SoT Design Using Three-terminal

Spendthrift: Machine learning based resource and frequency scaling for ambient energy harvesting nonvolatile processors

There and back again: Optimizing the interconnect in networks of memory cubes

TIME: A Training-in-memory Architecture for Memristor-based Deep Neural Networks

Adapting B⁺-Tree for Emerging Nonvolatile Memory-Based Main Memory

Hybrid Drowsy SRAM and STT-RAM Buffer Designs for Dark-Silicon-Aware NoC

Nonvolatile Processor Architectures: Efficient, Reliable Progress with Unstable Power

TSocket: Thermal sustainable power budgeting

A real-time and energy-efficient implementation of difference-of-Gaussian with flexible thin-film transistors

A unified memory network architecture for in-memory computing in commodity servers

An Instruction Set Architecture for Neural Networks

Architecture design with STT-RAM: Opportunities and challenges

Building a Low Latency, Highly Associative DRAM Cache with the Buffered Way Predictor

Cost analysis and cost-driven IP reuse methodology for SoC design based on 2.5D/3D integration

Cost and thermal analysis of high-performance 2.5D and 3D integrated circuit design space

Dynamic machine learning based matching of nonvolatile processor microarchitecture to harvested energy profile

Fine-granularity tile-level parallelism in non-volatile memory architecture with two-dimensional bank subdivision

LAP: Loop-Block Aware Inclusion Properties for Energy-Efficient Asymmetric Last Level Caches

Leveraging 3D technologies for hardware security: Opportunities and challenges

Mellow Writes: Extending Lifetime in Resistive Memories through Selective Slow Write Backs

MNSIM: Simulation platform for memristor-based neuromorphic computing system

Neural network transformation under hardware constraints

NVSim-CAM: A circuit-level simulator for emerging nonvolatile memory based content-addressable memory

NVSim-VX^s: An improved NVSim for variation aware STT-RAM simulation

ODESY: A novel 3T-3MTJ cell design with optimized area DEnsity, scalability and latencY

OSCAR: Orchestrating STT-RAM cache traffic for heterogeneous CPU-GPU architectures

Pinatubo: A processing-in-memory architecture for bulk bitwise operations in emerging non-volatile memories

PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory

Redesigning software and systems for non-volatile processors on self-powered devices

Scalable memory fabric for silicon interposer-based multi-core systems

Thermal-aware 3D design for side-channel information leakage

Utilizing 3D ICs in architectures for neural networks

A write-aware STTRAM-based register file architecture for GPGPU

Adaptive burst-writes (ABW): Memory requests scheduling to reduce write-induced interference

Buri: Scaling big-memory computing with hardware-based memory expansion

EECache: A comprehensive study on the architectural design for energy-efficient last-level caches in chip multiprocessors

Impact of cell failure on reliable cross-point resistive memory design

Impact of Write Pulse and Process Variation on 22 nm FinFET-Based STT-RAM Design: A Device-Architecture Co-Optimization Approach

Memory and storage system design with nonvolatile memory technologies

Nonvolatile Processor Architecture Exploration for Energy-Harvesting Applications

NVMain 2.0: A User-Friendly Memory Simulator to Model (Non-)Volatile Memory Systems

Whitespace-aware TSV arrangement in 3-D clock tree synthesis

Die-stacking Architecture

3D integration technology

Ambient energy harvesting nonvolatile processors: From circuit to system

Architecting 3D vertical resistive memory for next-generation storage systems

Architecture exploration for ambient energy harvesting nonvolatile processors

Core vs. uncore: The heart of darkness

DESTINY: A tool for modeling emerging 3D NVM and eDRAM caches

DimNoC: A dim silicon approach towards power-efficient on-chIP network

EECache: Exploiting design choices in energy-efficient last-level caches for chip multiprocessors

Enabling high-performance LPDDRx-compatible MRAM

Energy efficient RRAM spiking neural network for real time classification

Exploring memory controller configurations for many-core systems with 3D stacked DRAMs

FIRM: Fair and High-Performance Memory Control for Persistent Memory Systems

Heterogeneous architecture design with emerging 3D and non-volatile memory technologies

History-Assisted Adaptive-Granularity Caches (HAAG$) for high performance 3D DRAM architectures

Leveraging emerging nonvolatile memory in high-level synthesis with loop transformations

Making B⁺-tree efficient in PCM-based main memory

Modeling framework for cross-point resistive memory design emphasizing reliability and variability issues

Nonvolatile memory allocation and hierarchy optimization for high-level synthesis

Overcoming the challenges of crossbar resistive memory architectures

Using multi-level cell STT-RAM for fast and energy-efficient local checkpointing

Building and optimizing MRAM-based commodity memories

Endurance-aware cache line management for non-volatile caches

Exploration of electrical and novel optical chip-to-chip interconnects

On-chip hybrid power supply system for wireless sensor nodes

Optimizing the NoC slack through voltage and frequency scaling in hard real-time embedded systems

Preventing STT-RAM Last-Level Caches from Port Obstruction

PS3-RAM: A fast portable and scalable statistical STT-RAM reliability/energy analysis method

Testable cross-power domain interface (CPDI) circuit design in monolithic 3D technology

Emerging memory technologies: Design, architecture, and applications

NVSim: A circuit-level performance, energy, and area model for emerging non-volatile memory

3D RRAM design and benchmark with 3d NAND FLASH

3DLAT: TSV-based 3D ICs crosstalk minimization utilizing Less Adjacent Transition code

3D-SWIFT: A high-performance 3D-stacked wide IO DRAM

A cost benefit analysis: The impact of defect clustering on the necessity of pre-bond tests

Adaptive placement and migration policy for an STT-RAM-based hybrid cache

Building energy-efficient multi-level cell STT-MRAM based cache through dynamic data-resistance encoding

Compact models and model standard for 2.5D and 3D integration

CREAM: A concurrent-refresh-aware DRAM memory architecture

Design methodologies for 3D mixed signal integrated circuits: A practical 12-bit SAR ADC design case

Designing vertical bandwidth reconfigurable 3D NoCs for many core systems

Effcient region-aware P/G TSV planning for 3D ICs

Half-DRAM: A high-bandwidth and low-power DRAM architecture from the rethinking of fine-grained activation

Independently-controlled-gate FinFET 6T SRAM cell design for leakage current reduction and enhanced read access speed

Modeling and design analysis of 3D vertical resistive memory - A low cost cross-point architecture

NoC-Sprinting: Interconnect for fine-grained sprinting in the dark silicon era

NoΔ: Leveraging delta compression for end-to-end memory access in NoC based multicores

ProactiveDRAM: A DRAM-initiated retention management scheme

Reliability-aware cross-point resistive memory design

Run-Time Technique for Simultaneous Aging and Power Optimization in GPGPUs

SwimmingLane: A composite approach to mitigate voltage droop effects in 3D power delivery network

Thermal-Sustainable Power Budgeting for Dynamic Threading

TSV power supply array electromigration lifetime analysis in 3D ICS

A circuit-architecture co-optimization framework for exploring nonvolatile memory hierarchies

A synthesis algorithm for reconfigurable single-electron transistor arrays

Assessment of circuit optimization techniques under NBTI

Evaluation and mitigation of performance degradation under random telegraph noise for digital circuits

Optimizing gpu energy efficiency with 3d die-stacking graphics memory and reconfigurable memory interface

Through silicon via aware design planning for thermally efficient 3-D integrated circuits

WADE: Writeback-Aware Dynamic Cache Management for NVM-Based Main Memory System

Cost-driven 3D design optimization with metal layer reduction technique

CPDI: Cross-power-domain interface circuit design in monolithic 3D technology

Design of cross-point metal-oxide ReRAM emphasizing reliability and cost

Designing energy-efficient NoC for real-time embedded systems through slack optimization

i²WAP: Improving non-volatile cache lifetime by reducing inter- and intra-set write variations

Kiln: Closing the performance gap between systems with and without persistence support

Lazy precharge: An overhead-free method to reduce precharge overhead for memory parallelism improvement of DRAM system

Low power multi-level-cell resistive memory design with incomplete data mapping

OAP: An obstruction-aware cache management policy for STT-RAM last-level caches

TS-Router: On maximizing the Quality-of-Allocation in the On-Chip Network

TSV-aware topology generation for 3D Clock Tree Synthesis

Understanding the trade-offs in multi-level cell ReRAM memory design

Electrical characterization for intertier connections and timing analysis for 3-D ICs

NVSim: A circuit-level performance, energy, and area model for emerging nonvolatile memory

Parametric yield-driven resource binding in high-level synthesis with multi-V th/V dd library and device sizing

Performance/thermal-aware design of 3D-stacked L2 caches for CMPs

Power analysis attack resistance engineering by dynamic voltage and frequency scaling

3DHLS: Incorporating high-level synthesis in physical planning of three-dimensional (3D) ICs

Cache revive: Architecting volatile STT-RAM caches for enhanced performance in CMPs

Design trade-offs for high density cross-point resistive memory

Energy-efficient GPU design with reconfigurable in-package graphics memory

Low power memristor-based ReRAM design with error correcting code

Modeling and design exploration of FBDRAM as on-chip memory

NVMain: An architectural-level main memory simulator for emerging non-volatile memories

Optimizing bandwidth and power of graphics memory with hybrid memory technologies and adaptive data migration

Point and discard: A hard-error-tolerant architecture for non-volatile last level caches

PS3-RAM: A fast portable and scalable statistical STT-RAM reliability analysis method

Temporal performance degradation under RTN: Evaluation and mitigation for nanoscale circuits

Thermal-aware power network design for IR drop reduction in 3D ICs

Yield-aware time-efficient testing and self-fixing design for TSV-based 3D ICs

Exploiting heterogeneity for energy efficiency in chip multiprocessors

Hybrid checkpointing using emerging nonvolatile memories for future exascale systems

Leakage power and circuit aging cooptimization by gate replacement techniques

Modeling, Architecture, and Applications for Emerging Memory Technologies

Soft error rate analysis for combinational logic using an accurate electrical masking model

Stacking magnetic random access memory atop microprocessors: An architecture-level evaluation

Temperature-aware NBTI modeling and the impact of standby leakage reduction techniques on circuit performance degradation

Variation-Aware Task and Communication Mapping for MPSoC Architecture

Thermal-Aware 3D IC Designs

A frequent-value based PRAM memory architecture

AdaMS: Adaptive MLC/SLC phase-change memory design for file storage

An energy-efficient 3D CMP design with fine-grained voltage scaling

Analysis and mitigation of lateral thermal blockage effect of through-silicon-via in 3D IC designs

Architecting NoCs for Stacked 3D STT-RAM Caches in CMPs

Automated mapping for reconfigurable single-electron transistor arrays

Bandwidth-aware reconfigurable cache design with hybrid memory technologies

Design implications of memristor-based RRAM cross-point structures

Device-architecture co-optimization of STT-RAM based memory for low power embedded systems

Enabling architectural innovations using non-volatile memory

Enabling quality-of-service in nanophotonic network-on-chip

Energy-efficient multi-level cell phase-change memory system with data encoding

Exploring the vulnerability of CMPs to soft errors with 3D stacked non-volatile memory

F²BFLY: An on-chip free-space optical network with wavelength-switching

Impact of circuit degradation on FPGA design security

Moguls: a Model to Explore Memory Hierarchy for Throughput Computing

MorphCache: A reconfigurable adaptive multi-level cache hierarchy

On-chip hybrid power supply system for wireless sensor nodes

System-level design space exploration for three-dimensional (3D) SoCs

3D stacked microprocessor: Are we there yet?

Design exploration of hybrid caches with disparate memory technologies

Fabrication cost analysis and cost-aware design space exploration for 3-D ICs

Test-access mechanism optimization for core-based three-dimensional SOCs

Total power optimization for combinational logic using genetic algorithms

Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance

3D memory stacking for fast checkpointing/restore applications

3D-NonFAR: Three-dimensional non-volatile FPGA architecture using phase change memory

A 3D SoC design for H.264 application with on-chip DRAM stacking

A customized design of DRAM controller for on-chip 3D DRAM stacking

Accelerating adaptive background subtraction with GPU and CBEA architecture

Cost-aware three-dimensional (3D) many-core multiprocessor design

Cost-driven 3D integration with interconnect layers

Cost-effective integration of three-dimensional (3D) ICs emphasizing testing cost analysis

Energy- and endurance-aware design of phase change memory caches

Energy and performance driven circuit design for emerging phase-change memory

Evaluation of using inductive/capacitive-coupling vertical interconnects in 3D network-on-chip

Hybrid Solid-State Storage Architecture for Performance, Energy Consumption and Lifetime Improvement

Impact of process variations on emerging memristor

LOFT: A high performance network-on-chip providing quality-of-service support

Low-power dual-element memristor based memory design

Minimizing leakage power in aging-bounded high-level synthesis with design time multi-Vth assignment

Modeling TSV open defects in 3D-stacked DRAM

Parametric yield driven resource binding in behavioral synthesis with multi-Vth/Vdd library

Processor architecture design using 3D integration technology

Simple but effective heterogeneous main memory with on-chip memory controller support

Three-dimensional integrated circuits (3D IC) floorplan and power/ground network co-synthesis

Modeling soft errors at the device and logic levels for combinational circuits

New-age: A negative bias temperature instability-estimation framework for microarchitectural components

Process variation-aware adaptive cache architecture and management

Scan-chain design and optimization for three-dimensional integrated circuits

Statistical High-Level Synthesis under Process Variability

Temperature-aware NBTI modeling techniques in digital circuits

Three-dimensional IC: Design, CAD, and Architecture

3D Network-on-chip Architecture

System-level Cost Analsysis and Design Exploration for 3D ICs

A criticality-driven microarchitectural three dimensional (3D) floorplanner

A framework for estimating NBTI degradation of microarchitectural components

A Novel MRAM Stacking Architecture for Chip-multiprocessors (CMP)

Gate replacement techniques for simultaneous leakage and aging optimization

Hybrid cache architecture with disparate memory technologies

Intrinsic NBTI-variability aware statistical pipeline performance assessment and tuning

Leveraging 3D PCRAM technologies to reduce checkpoint overhead for future exascale systems

NBTI-Aware statistical circuit delay assessment

Networks-on-chip in emerging interconnect paradigms: Advantages and challenges

On the effcacy of Input Vector Control to mitigate NBTI effects and leakage power

PCRAMsim: System-level performance, energy, and area modeling for phase-change RAM

Power and performance of read-write aware hybrid caches with non-volatile memories

System-level cost analysis and design exploration for three-dimensional integrated circuits (3D ICs)

Tolerating process variations in high-level synthesis using transparent latches

Variation-aware resource sharing and binding in behavioral synthesis

Case study of reliability-aware and low-power design

Design space exploration for 3-D Cache

Thermal neutron induced soft error rate measurement in semiconductor memories and circuits

Toward increasing FPGA lifetime

A variation aware high level synthesis framework

Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement

Cost Analysis and Cost-driven EDA flow for 3D ICs

ILP-based scheme for timing variation-aware scheduling and resource binding

MIRA: A multi-layered on-chip interconnect router architecture

Power optimization for FinFET-based circuits using genetic algorithms

Test-access mechanism optimization for core-based three-dimensional SOCs

Thermal-aware design considerations for application-specific instruction set processor

Thermal-aware reliability analysis for platform FPGAs

Variability-driven module selection with joint design time optimization and post-silicon tuning

Code compression for VLIW embedded systems using a self-generating table

Code decompression unit design for VLIW embedded processors

On-chip Bus Thermal Analysis and Optimization

Processor design in 3D die-stacking technologies

Reliability-aware co-synthesis for embedded systems

A novel criticality computation method in statistical timing analysis

A novel dimensionally-decomposed router for on-chip communication in 3D architectures

A novel gate-level NBTI delay degradation model with stacking effect

Architecting microprocessor components in 3D design space

Collaborative VLSI-CAD instruction in the digital sandbox

FPGA routing architecture analysis under variations

Modeling of PMOS NBTI effect considering temperature variation

Scan chain design for three-dimensional integrated circuits (3D ICs)

Soft error rate analysis for combinational logic using an accurate electrical masking model

Temperature-aware NBTI modeling and the impact of input vector control on performance degradation

Variation analysis of CAM cells

Variation Impact on SER of Combinatorial Circuits

Variation-aware task allocation and scheduling for MPSoC

Code compression for embedded VLIW processors using variable-to-fixed coding

Design space exploration for 3D architectures

Reliability concerns in embedded system designs

Temperature-aware task allocation and scheduling for embedded Multiprocessor Systems-on-Chip (MPSoC) design

A hybrid SoC interconnect with dynamic TDMA-based transaction-less buses and on-chip networks

Analysis of subthreshold finfet circuits for ultra-low power design

Crosstalk-aware energy efficient encoding for instruction bus through code compression

Delay and energy efficient data transmission for on-chip buses

Dependability analysis of nano-scale FinFET circuits

Design and management of 3D chip multiprocessors using network-in-memory

Effect of power optimizations on soft error rate

FLAW: FPGA lifetime awareness

Guaranteeing performance yield in high-level synthesis

Interconnect and thermal-aware floorplanning for 3D microprocessors

Leakage optimized DECAP design for FPGAs

Modeling the impact of process variation on critical charge distribution

On-chip bus thermal analysis and optimization

Optimal topology exploration for application-specific 3D architectures

Reliability-aware SOC voltage Islands partition and floorplan

SEAT-LA: A soft error analysis tool for combinational logic

Accurate stacking effect macro-modeling of leakage power in sub-100nm circuits

Adaptive power management in Software Radios using resolution adaptive analog to digital converters

An ILP formulation for reliability-oriented high-level synthesis

An instruction-level analytical power model for designing the low power systems on a chip

Evaluation of thermal-aware design techniques for microprocessors

FD-HGAC: A hybrid heuristic/genetic algorithm hardware/software co-synthesis framework with fault detection

Influence of leakage reduction techniques on delay/leakage uncertainty

Leakage-aware interconnect for on-chip network

Low-leakage robust SRAM cell design for sub-100nm technologies

Power attack resistant cryptosystem design: A dynamic voltage and frequency switching approach

Reliability-centric hardware/software co-design

Reliability-centric high-level synthesis

Temperature-aware voltage islands architecting in system-on-chip design

Temperature-sensitive loop parallelization for chip multiprocessors

Thermal-Aware Allocation and Scheduling for Systems-on-a-Chip Design

Thermal-aware floorplanning using genetic algorithms

Three-dimensional cache design exploration using 3DCacti

Design of a nanosensor array architecture

Improving soft-error tolerance of FPGA configuration bits

LZW-based code compression for VLIW embedded systems

Reliability-aware co-synthesis for embedded systems

The effect of threshold voltages on the soft error rate

Thermal-aware IP visualization and placement for networks-on-chip architecture

Total power optimization through simultaneously multiple-V_DD multiple-V_TH assignment and device sizing with stack forcing

Augmenting Platform-based Design with Synthesis Tools

Analysis of Two Code Compression Algorithms for Embedded Systems

Code compression using variable-to-fixed coding based on arithmetic coding

Profile-driven Code Compression

Code compression for VLIW processors using variable-to-fixed coding

Allocation and scheduling of conditional task graph in hardware/software co-synthesis

ASICosyn: Co-synthesis of conditional task graphs with custom ASICs

Code compression for VLIW processors

Compression ratio and decompression overhead tradeoffs in code compression for VLIW architectures

CAD Techniques for Multimedia System Design

Co-synthesis with custom ASICs

An Adaptive 3T-3MTJ Memory Cell Design for STT-MRAM-Based LLCs

Article

Crossbar-aware neural network pruning

Article

Die Stacking Is Happening

Article

Exploring Core and Cache Hierarchy Bottlenecks in Graph Processing Workloads

Article

IAA: Incidental Approximate Architectures for Extremely Energy-Constrained Energy Harvesting Scenarios using IoT Nonvolatile Processors

Article

Memory that never forgets: Emerging nonvolatile memory and the implication for architecture design

Article

Mitigating BTI-induced degradation in STT-MRAM sensing schemes

Article

MNSIM: Simulation Platform for Memristor-Based Neuromorphic Computing System

Article

Performance evaluation and optimization of HBM-Enabled GPU for data-intensive applications

Article

Securing Emerging Nonvolatile Main Memory with Fast and Energy-Efficient AES In-Memory Implementation

Article

Stuck-at Fault Tolerance in RRAM Computing Systems

Article

AIM: Fast and energy-efficient AES in-memory implementation for emerging non-volatile main memory

Conference paper

Bridging the gap between neural networks and neuromorphic hardware with a neural network compiler

Conference paper

NEOFog: Nonvolatility-exploiting optimizations for fog computing

Conference paper

Packet pump: Overcoming network bottleneck in on-chip interconnects for GPGPUs

Conference paper

Persistence parallelism optimization: A holistic approach from Memory Bus to RDMA Network

Conference paper

RADAR: A 3D-ReRAM based DNA alignment accelerator architecture

Conference paper

SCOPE: A stochastic computing engine for DRAM-based in-situ accelerator

Conference paper

SNrram: An efficient sparse neural network computation architecture based on resistive random-access memory

Conference paper

A Study on Practically Unlimited Endurance of STT-MRAM

Article

DLAU: A scalable deep learning accelerator unit on FPGA

Article

Dynamic power and energy management for energy harvesting nonvolatile processor systems

Article

Overview of 3-D Architecture Design Opportunities and Techniques

Article

Software-Hardware Codesign for Efficient Neural Network Acceleration

Article

Thermomechanical Stress-Aware Management for 3-D IC Designs

Article

NoC-aware computational sprinting

Book chapter

A 462GOPs/J RRAM-based nonvolatile intelligent processor for energy harvesting IoE system featuring nonvolatile logics and processing-in-memory

Conference paper

Building energy-efficient multi-level cell STT-RAM caches with data compression

Conference paper

Computation-oriented fault-tolerance schemes for RRAM computing systems

Conference paper

Cost-effective design of scalable high-performance systems using active and passive interposers

Conference paper

DRISA: A DRAM-based reconfigurable in-situ accelerator

Conference paper

Incidental computing on IoT nonvolatile processors

Conference paper

Performance evaluation and optimization of HBM-Enabled GPU for data-intensive applications

Conference paper

Security threats and countermeasures in three-dimensional integrated circuits

Conference paper

SoT Design Using Three-terminal

Conference paper

Spendthrift: Machine learning based resource and frequency scaling for ambient energy harvesting nonvolatile processors

Conference paper

There and back again: Optimizing the interconnect in networks of memory cubes

Conference paper

TIME: A Training-in-memory Architecture for Memristor-based Deep Neural Networks

Conference paper

Adapting B⁺-Tree for Emerging Nonvolatile Memory-Based Main Memory

Article

Hybrid Drowsy SRAM and STT-RAM Buffer Designs for Dark-Silicon-Aware NoC

Article

Nonvolatile Processor Architectures: Efficient, Reliable Progress with Unstable Power

Article

TSocket: Thermal sustainable power budgeting

Article

A real-time and energy-efficient implementation of difference-of-Gaussian with flexible thin-film transistors

Conference paper

A unified memory network architecture for in-memory computing in commodity servers

Conference paper

An Instruction Set Architecture for Neural Networks

Conference paper

Architecture design with STT-RAM: Opportunities and challenges

Conference paper

Building a Low Latency, Highly Associative DRAM Cache with the Buffered Way Predictor

Conference paper

Cost analysis and cost-driven IP reuse methodology for SoC design based on 2.5D/3D integration

Conference paper

Cost and thermal analysis of high-performance 2.5D and 3D integrated circuit design space

Conference paper

Dynamic machine learning based matching of nonvolatile processor microarchitecture to harvested energy profile

Conference paper

Fine-granularity tile-level parallelism in non-volatile memory architecture with two-dimensional bank subdivision

Conference paper

LAP: Loop-Block Aware Inclusion Properties for Energy-Efficient Asymmetric Last Level Caches

Conference paper

Leveraging 3D technologies for hardware security: Opportunities and challenges

Conference paper

Mellow Writes: Extending Lifetime in Resistive Memories through Selective Slow Write Backs

Conference paper

MNSIM: Simulation platform for memristor-based neuromorphic computing system

Conference paper

Neural network transformation under hardware constraints

Conference paper

NVSim-CAM: A circuit-level simulator for emerging nonvolatile memory based content-addressable memory

Conference paper

NVSim-VX^s: An improved NVSim for variation aware STT-RAM simulation

Conference paper

ODESY: A novel 3T-3MTJ cell design with optimized area DEnsity, scalability and latencY

Conference paper

OSCAR: Orchestrating STT-RAM cache traffic for heterogeneous CPU-GPU architectures

Conference paper

Pinatubo: A processing-in-memory architecture for bulk bitwise operations in emerging non-volatile memories

Conference paper

PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory

Conference paper

Redesigning software and systems for non-volatile processors on self-powered devices

Conference paper

Scalable memory fabric for silicon interposer-based multi-core systems

Conference paper

Thermal-aware 3D design for side-channel information leakage

Conference paper

Utilizing 3D ICs in architectures for neural networks

Conference paper

A write-aware STTRAM-based register file architecture for GPGPU

Article

Adaptive burst-writes (ABW): Memory requests scheduling to reduce write-induced interference

Article

Buri: Scaling big-memory computing with hardware-based memory expansion

Article

EECache: A comprehensive study on the architectural design for energy-efficient last-level caches in chip multiprocessors

Article

Impact of cell failure on reliable cross-point resistive memory design

Article

Impact of Write Pulse and Process Variation on 22 nm FinFET-Based STT-RAM Design: A Device-Architecture Co-Optimization Approach

Article

Memory and storage system design with nonvolatile memory technologies

Article

Nonvolatile Processor Architecture Exploration for Energy-Harvesting Applications

Article

NVMain 2.0: A User-Friendly Memory Simulator to Model (Non-)Volatile Memory Systems

Article

Whitespace-aware TSV arrangement in 3-D clock tree synthesis

Article

Die-stacking Architecture

Book

3D integration technology

Book chapter

Ambient energy harvesting nonvolatile processors: From circuit to system

Conference paper

Architecting 3D vertical resistive memory for next-generation storage systems

Conference paper

Architecture exploration for ambient energy harvesting nonvolatile processors

Conference paper

Core vs. uncore: The heart of darkness

Conference paper

DESTINY: A tool for modeling emerging 3D NVM and eDRAM caches

Conference paper

DimNoC: A dim silicon approach towards power-efficient on-chIP network

Conference paper

EECache: Exploiting design choices in energy-efficient last-level caches for chip multiprocessors

Conference paper

Enabling high-performance LPDDRx-compatible MRAM

Conference paper

Energy efficient RRAM spiking neural network for real time classification

Conference paper

Exploring memory controller configurations for many-core systems with 3D stacked DRAMs

Conference paper

FIRM: Fair and High-Performance Memory Control for Persistent Memory Systems

Conference paper

Heterogeneous architecture design with emerging 3D and non-volatile memory technologies

Conference paper

History-Assisted Adaptive-Granularity Caches (HAAG$) for high performance 3D DRAM architectures

Conference paper

Leveraging emerging nonvolatile memory in high-level synthesis with loop transformations

Conference paper

Making B⁺-tree efficient in PCM-based main memory

Conference paper

Modeling framework for cross-point resistive memory design emphasizing reliability and variability issues

Conference paper

Nonvolatile memory allocation and hierarchy optimization for high-level synthesis

Conference paper

Overcoming the challenges of crossbar resistive memory architectures

Conference paper

Using multi-level cell STT-RAM for fast and energy-efficient local checkpointing

Conference paper

Building and optimizing MRAM-based commodity memories

Article

Endurance-aware cache line management for non-volatile caches

Article

Exploration of electrical and novel optical chip-to-chip interconnects

Article

On-chip hybrid power supply system for wireless sensor nodes

Article

Optimizing the NoC slack through voltage and frequency scaling in hard real-time embedded systems

Article

Preventing STT-RAM Last-Level Caches from Port Obstruction

Article

PS3-RAM: A fast portable and scalable statistical STT-RAM reliability/energy analysis method

Article

Testable cross-power domain interface (CPDI) circuit design in monolithic 3D technology

Article

Emerging memory technologies: Design, architecture, and applications

Book

NVSim: A circuit-level performance, energy, and area model for emerging non-volatile memory

Book chapter

3D RRAM design and benchmark with 3d NAND FLASH

Conference paper

3DLAT: TSV-based 3D ICs crosstalk minimization utilizing Less Adjacent Transition code

Conference paper

3D-SWIFT: A high-performance 3D-stacked wide IO DRAM

Conference paper

A cost benefit analysis: The impact of defect clustering on the necessity of pre-bond tests

Conference paper

Adaptive placement and migration policy for an STT-RAM-based hybrid cache

Conference paper

Building energy-efficient multi-level cell STT-MRAM based cache through dynamic data-resistance encoding

Conference paper

Compact models and model standard for 2.5D and 3D integration

Conference paper

CREAM: A concurrent-refresh-aware DRAM memory architecture

Conference paper

Design methodologies for 3D mixed signal integrated circuits: A practical 12-bit SAR ADC design case

Conference paper

Designing vertical bandwidth reconfigurable 3D NoCs for many core systems

Conference paper

Effcient region-aware P/G TSV planning for 3D ICs

Conference paper

Half-DRAM: A high-bandwidth and low-power DRAM architecture from the rethinking of fine-grained activation

Conference paper

Independently-controlled-gate FinFET 6T SRAM cell design for leakage current reduction and enhanced read access speed

Conference paper

Modeling and design analysis of 3D vertical resistive memory - A low cost cross-point architecture

Conference paper

NoC-Sprinting: Interconnect for fine-grained sprinting in the dark silicon era

Conference paper

NoΔ: Leveraging delta compression for end-to-end memory access in NoC based multicores

Conference paper

ProactiveDRAM: A DRAM-initiated retention management scheme

Conference paper

Reliability-aware cross-point resistive memory design

Conference paper

Run-Time Technique for Simultaneous Aging and Power Optimization in GPGPUs

Conference paper

SwimmingLane: A composite approach to mitigate voltage droop effects in 3D power delivery network

Conference paper

Thermal-Sustainable Power Budgeting for Dynamic Threading

Conference paper

TSV power supply array electromigration lifetime analysis in 3D ICS

Conference paper

A circuit-architecture co-optimization framework for exploring nonvolatile memory hierarchies

Article

A synthesis algorithm for reconfigurable single-electron transistor arrays

Article

Assessment of circuit optimization techniques under NBTI

Article

Evaluation and mitigation of performance degradation under random telegraph noise for digital circuits

Article

Optimizing gpu energy efficiency with 3d die-stacking graphics memory and reconfigurable memory interface

Article

Through silicon via aware design planning for thermally efficient 3-D integrated circuits

Article

WADE: Writeback-Aware Dynamic Cache Management for NVM-Based Main Memory System

Article

Cost-driven 3D design optimization with metal layer reduction technique

Conference paper

CPDI: Cross-power-domain interface circuit design in monolithic 3D technology

Conference paper

Design of cross-point metal-oxide ReRAM emphasizing reliability and cost

Conference paper

Designing energy-efficient NoC for real-time embedded systems through slack optimization

Conference paper

i²WAP: Improving non-volatile cache lifetime by reducing inter- and intra-set write variations

Conference paper

Kiln: Closing the performance gap between systems with and without persistence support

Conference paper

Lazy precharge: An overhead-free method to reduce precharge overhead for memory parallelism improvement of DRAM system

Conference paper

Low power multi-level-cell resistive memory design with incomplete data mapping

Conference paper

OAP: An obstruction-aware cache management policy for STT-RAM last-level caches

Conference paper

TS-Router: On maximizing the Quality-of-Allocation in the On-Chip Network

Conference paper

TSV-aware topology generation for 3D Clock Tree Synthesis

Conference paper

Understanding the trade-offs in multi-level cell ReRAM memory design

Conference paper

Electrical characterization for intertier connections and timing analysis for 3-D ICs

Article

NVSim: A circuit-level performance, energy, and area model for emerging nonvolatile memory

Article

Parametric yield-driven resource binding in high-level synthesis with multi-V th/V dd library and device sizing

Article

Performance/thermal-aware design of 3D-stacked L2 caches for CMPs

Article

Power analysis attack resistance engineering by dynamic voltage and frequency scaling

Article

3DHLS: Incorporating high-level synthesis in physical planning of three-dimensional (3D) ICs

Conference paper

Cache revive: Architecting volatile STT-RAM caches for enhanced performance in CMPs

Conference paper

Design trade-offs for high density cross-point resistive memory

Conference paper

Energy-efficient GPU design with reconfigurable in-package graphics memory

Conference paper

Low power memristor-based ReRAM design with error correcting code

Conference paper

Modeling and design exploration of FBDRAM as on-chip memory

Conference paper

NVMain: An architectural-level main memory simulator for emerging non-volatile memories

Conference paper

Optimizing bandwidth and power of graphics memory with hybrid memory technologies and adaptive data migration

Conference paper

Point and discard: A hard-error-tolerant architecture for non-volatile last level caches

Conference paper

PS3-RAM: A fast portable and scalable statistical STT-RAM reliability analysis method

Conference paper

Temporal performance degradation under RTN: Evaluation and mitigation for nanoscale circuits

Conference paper

Thermal-aware power network design for IR drop reduction in 3D ICs

Conference paper

Yield-aware time-efficient testing and self-fixing design for TSV-based 3D ICs

Conference paper

Exploiting heterogeneity for energy efficiency in chip multiprocessors

Article

Hybrid checkpointing using emerging nonvolatile memories for future exascale systems

Article

Leakage power and circuit aging cooptimization by gate replacement techniques

Article

Modeling, Architecture, and Applications for Emerging Memory Technologies

Article

Soft error rate analysis for combinational logic using an accurate electrical masking model

Article

Stacking magnetic random access memory atop microprocessors: An architecture-level evaluation

Article

Temperature-aware NBTI modeling and the impact of standby leakage reduction techniques on circuit performance degradation

Article

Variation-Aware Task and Communication Mapping for MPSoC Architecture

Article

Thermal-Aware 3D IC Designs

Book chapter

A frequent-value based PRAM memory architecture

Conference paper

AdaMS: Adaptive MLC/SLC phase-change memory design for file storage

Conference paper

An energy-efficient 3D CMP design with fine-grained voltage scaling

Conference paper

Analysis and mitigation of lateral thermal blockage effect of through-silicon-via in 3D IC designs

Conference paper

Architecting NoCs for Stacked 3D STT-RAM Caches in CMPs

Conference paper

Automated mapping for reconfigurable single-electron transistor arrays

Conference paper

Bandwidth-aware reconfigurable cache design with hybrid memory technologies

Conference paper

Design implications of memristor-based RRAM cross-point structures

Conference paper

Device-architecture co-optimization of STT-RAM based memory for low power embedded systems

Conference paper

Enabling architectural innovations using non-volatile memory

Conference paper

Enabling quality-of-service in nanophotonic network-on-chip

Conference paper

Energy-efficient multi-level cell phase-change memory system with data encoding

Conference paper

Exploring the vulnerability of CMPs to soft errors with 3D stacked non-volatile memory

Conference paper

F²BFLY: An on-chip free-space optical network with wavelength-switching

Conference paper

Impact of circuit degradation on FPGA design security

Conference paper

Moguls: a Model to Explore Memory Hierarchy for Throughput Computing

Conference paper

MorphCache: A reconfigurable adaptive multi-level cache hierarchy

Conference paper

On-chip hybrid power supply system for wireless sensor nodes

Conference paper

System-level design space exploration for three-dimensional (3D) SoCs

Conference paper

3D stacked microprocessor: Are we there yet?

Article

Design exploration of hybrid caches with disparate memory technologies

Article

Fabrication cost analysis and cost-aware design space exploration for 3-D ICs

Article

Test-access mechanism optimization for core-based three-dimensional SOCs

Article

Total power optimization for combinational logic using genetic algorithms

Article

Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance

Article

3D memory stacking for fast checkpointing/restore applications

Conference paper

3D-NonFAR: Three-dimensional non-volatile FPGA architecture using phase change memory

Conference paper

A 3D SoC design for H.264 application with on-chip DRAM stacking

Conference paper

A customized design of DRAM controller for on-chip 3D DRAM stacking

Conference paper

Accelerating adaptive background subtraction with GPU and CBEA architecture

Conference paper

Cost-aware three-dimensional (3D) many-core multiprocessor design

Conference paper

Cost-driven 3D integration with interconnect layers

Conference paper

Cost-effective integration of three-dimensional (3D) ICs emphasizing testing cost analysis

Conference paper

Energy- and endurance-aware design of phase change memory caches

Conference paper

Energy and performance driven circuit design for emerging phase-change memory

Conference paper

Evaluation of using inductive/capacitive-coupling vertical interconnects in 3D network-on-chip

Conference paper

Hybrid Solid-State Storage Architecture for Performance, Energy Consumption and Lifetime Improvement

Conference paper

Impact of process variations on emerging memristor

Conference paper

LOFT: A high performance network-on-chip providing quality-of-service support

Conference paper

Low-power dual-element memristor based memory design

Conference paper

Minimizing leakage power in aging-bounded high-level synthesis with design time multi-Vth assignment

Conference paper

Modeling TSV open defects in 3D-stacked DRAM

Conference paper

Parametric yield driven resource binding in behavioral synthesis with multi-Vth/Vdd library

Conference paper

Processor architecture design using 3D integration technology

Conference paper

Simple but effective heterogeneous main memory with on-chip memory controller support

Conference paper

Three-dimensional integrated circuits (3D IC) floorplan and power/ground network co-synthesis

Conference paper

Modeling soft errors at the device and logic levels for combinational circuits

Article

New-age: A negative bias temperature instability-estimation framework for microarchitectural components

Article

Process variation-aware adaptive cache architecture and management

Article

Scan-chain design and optimization for three-dimensional integrated circuits

Article

Statistical High-Level Synthesis under Process Variability

Article

Temperature-aware NBTI modeling techniques in digital circuits

Article

Three-dimensional IC: Design, CAD, and Architecture

Book

3D Network-on-chip Architecture

Book chapter

System-level Cost Analsysis and Design Exploration for 3D ICs

Book chapter

A criticality-driven microarchitectural three dimensional (3D) floorplanner

Conference paper

A framework for estimating NBTI degradation of microarchitectural components

Conference paper

A Novel MRAM Stacking Architecture for Chip-multiprocessors (CMP)

Conference paper

Gate replacement techniques for simultaneous leakage and aging optimization

Conference paper

Hybrid cache architecture with disparate memory technologies

Conference paper

Intrinsic NBTI-variability aware statistical pipeline performance assessment and tuning

Conference paper

Leveraging 3D PCRAM technologies to reduce checkpoint overhead for future exascale systems

Conference paper

NBTI-Aware statistical circuit delay assessment

Conference paper

Networks-on-chip in emerging interconnect paradigms: Advantages and challenges

Conference paper

On the effcacy of Input Vector Control to mitigate NBTI effects and leakage power

Conference paper

PCRAMsim: System-level performance, energy, and area modeling for phase-change RAM

Conference paper

Power and performance of read-write aware hybrid caches with non-volatile memories

Conference paper

System-level cost analysis and design exploration for three-dimensional integrated circuits (3D ICs)

Conference paper

Tolerating process variations in high-level synthesis using transparent latches

Conference paper

Variation-aware resource sharing and binding in behavioral synthesis

Conference paper

Case study of reliability-aware and low-power design

Article

Design space exploration for 3-D Cache

Article

Thermal neutron induced soft error rate measurement in semiconductor memories and circuits

Article

Toward increasing FPGA lifetime

Article

A variation aware high level synthesis framework

Conference paper

Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement

Conference paper

Cost Analysis and Cost-driven EDA flow for 3D ICs

Conference paper

ILP-based scheme for timing variation-aware scheduling and resource binding

Conference paper

MIRA: A multi-layered on-chip interconnect router architecture

Conference paper

Power optimization for FinFET-based circuits using genetic algorithms

Conference paper

Test-access mechanism optimization for core-based three-dimensional SOCs

Conference paper

Thermal-aware design considerations for application-specific instruction set processor

Conference paper

Thermal-aware reliability analysis for platform FPGAs

Conference paper

Variability-driven module selection with joint design time optimization and post-silicon tuning

Conference paper

Code compression for VLIW embedded systems using a self-generating table

Article

Code decompression unit design for VLIW embedded processors

Article

On-chip Bus Thermal Analysis and Optimization

Article

Processor design in 3D die-stacking technologies

Article

Reliability-aware co-synthesis for embedded systems

Article

A novel criticality computation method in statistical timing analysis

Conference paper

A novel dimensionally-decomposed router for on-chip communication in 3D architectures

Conference paper

A novel gate-level NBTI delay degradation model with stacking effect

Conference paper

Architecting microprocessor components in 3D design space

Conference paper

Collaborative VLSI-CAD instruction in the digital sandbox

Conference paper

FPGA routing architecture analysis under variations

Conference paper

Modeling of PMOS NBTI effect considering temperature variation

Conference paper

Scan chain design for three-dimensional integrated circuits (3D ICs)

Conference paper

Soft error rate analysis for combinational logic using an accurate electrical masking model

Conference paper

Temperature-aware NBTI modeling and the impact of input vector control on performance degradation

Conference paper

Variation analysis of CAM cells

Conference paper

Variation Impact on SER of Combinatorial Circuits

Conference paper

Variation-aware task allocation and scheduling for MPSoC

Conference paper

Code compression for embedded VLIW processors using variable-to-fixed coding

Article

Design space exploration for 3D architectures

Article

Reliability concerns in embedded system designs

Article

Temperature-aware task allocation and scheduling for embedded Multiprocessor Systems-on-Chip (MPSoC) design

Article

A hybrid SoC interconnect with dynamic TDMA-based transaction-less buses and on-chip networks

Conference paper

Analysis of subthreshold finfet circuits for ultra-low power design

Conference paper

Crosstalk-aware energy efficient encoding for instruction bus through code compression

Conference paper

Delay and energy efficient data transmission for on-chip buses

Conference paper

Dependability analysis of nano-scale FinFET circuits

Conference paper

Design and management of 3D chip multiprocessors using network-in-memory

Conference paper

Effect of power optimizations on soft error rate

Conference paper

FLAW: FPGA lifetime awareness

Conference paper

Guaranteeing performance yield in high-level synthesis

Conference paper

Interconnect and thermal-aware floorplanning for 3D microprocessors

Conference paper

Leakage optimized DECAP design for FPGAs

Conference paper

Modeling the impact of process variation on critical charge distribution

Conference paper

On-chip bus thermal analysis and optimization

Conference paper

Optimal topology exploration for application-specific 3D architectures

Conference paper

Reliability-aware SOC voltage Islands partition and floorplan

Conference paper

SEAT-LA: A soft error analysis tool for combinational logic

Conference paper

Accurate stacking effect macro-modeling of leakage power in sub-100nm circuits

Conference paper

Adaptive power management in Software Radios using resolution adaptive analog to digital converters

Conference paper

An ILP formulation for reliability-oriented high-level synthesis

Conference paper

An instruction-level analytical power model for designing the low power systems on a chip

Conference paper

Evaluation of thermal-aware design techniques for microprocessors

Conference paper

FD-HGAC: A hybrid heuristic/genetic algorithm hardware/software co-synthesis framework with fault detection

Conference paper

Influence of leakage reduction techniques on delay/leakage uncertainty

Conference paper

Leakage-aware interconnect for on-chip network

Conference paper

Low-leakage robust SRAM cell design for sub-100nm technologies

Conference paper

Power attack resistant cryptosystem design: A dynamic voltage and frequency switching approach

Conference paper

Reliability-centric hardware/software co-design

Conference paper

Reliability-centric high-level synthesis

Conference paper

Temperature-aware voltage islands architecting in system-on-chip design

Conference paper

Temperature-sensitive loop parallelization for chip multiprocessors

Conference paper

Thermal-Aware Allocation and Scheduling for Systems-on-a-Chip Design

Conference paper

Thermal-aware floorplanning using genetic algorithms

Conference paper

Three-dimensional cache design exploration using 3DCacti

Conference paper

Design of a nanosensor array architecture

Conference paper

Improving soft-error tolerance of FPGA configuration bits

Conference paper

LZW-based code compression for VLIW embedded systems

Conference paper

Reliability-aware co-synthesis for embedded systems

Conference paper

The effect of threshold voltages on the soft error rate

Conference paper

Thermal-aware IP visualization and placement for networks-on-chip architecture

Conference paper

Total power optimization through simultaneously multiple-V_DD multiple-V_TH assignment and device sizing with stack forcing

Conference paper

Augmenting Platform-based Design with Synthesis Tools

Article

Analysis of Two Code Compression Algorithms for Embedded Systems

Conference paper

Code compression using variable-to-fixed coding based on arithmetic coding

Conference paper

Profile-driven Code Compression

Conference paper

Code compression for VLIW processors using variable-to-fixed coding

Conference paper

Allocation and scheduling of conditional task graph in hardware/software co-synthesis

Conference paper

ASICosyn: Co-synthesis of conditional task graphs with custom ASICs

Conference paper

Code compression for VLIW processors

Conference paper

Compression ratio and decompression overhead tradeoffs in code compression for VLIW architectures

Conference paper

CAD Techniques for Multimedia System Design

Conference paper

Co-synthesis with custom ASICs

Conference paper