PhD in Computer Engineering
Princeton University, 2009
Article
Boosting the Convergence of Reinforcement Learning-based Auto-pruning Using Historical Data
Article
Data-Pattern-Based Predictive On-Chip Power Meter in DNN Accelerator
Article
Deep Reinforcement Learning-Based Power Management for Chiplet-Based Multicore Systems
Article
Unveiling the Advantages of Full Coherency Architecture for FPSoC Systems
Article
A Modular Branch Predictor Performance Analysis Framework for Fast Design Space Exploration
Conference paper
Collaborative Coalescing of Redundant Memory Access for GPU System
Conference paper
DeepIC3: Guiding IC3 Algorithms by Graph Neural Network Clause Prediction
Conference paper
Designing and Accelerating Spiking Neural Network Based on High-Level Synthesis
Conference paper
GraFlex: Flexible Graph Processing on FPGAs through Customized Scalable Interconnection Network
Conference paper
PC-oriented Prediction-based Runtime Power Management for GPGPU using Knowledge Transfer
Conference paper
PhotonNTT: Energy-efficient Parallel Photonic Number Theoretic Transform Accelerator
Conference paper
SCNoCs: An Adaptive Heterogeneous Multi-NoC with Selective Compression and Power Gating
Conference paper
Towards Scalable GPU System with Silicon Photonic Chiplet
Conference paper
Accelerating Loop-Oriented RTL Simulation with Code Instrumentation
Article
Article
HL-Pow: Learning-Assisted Pre-RTL Power Modeling and Optimization for FPGA HLS
Article
Optimizing for In-Memory Deep Learning With Emerging Memory Technology
Article
ACGraph: Accelerating Streaming Graph Processing via Dependence Hierarchy
Conference paper
Area-efficient and Scalable Accelerator for Number Theoretic Transform Modelled on Tensor Products
Conference paper
Cache Side-channel Attacks and Defenses of the Sliding Window Algorithm in TEEs
Conference paper
DiffLo: A Graph-based Method for Functional Discrepancy Localization in High-level Synthesis.
Conference paper
FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAs
Conference paper
Conference paper
PertNAS: Architectural Perturbations for Memory-Efficient Neural Architecture Search
Conference paper
PROPHET: Predictive On-Chip Power Meter in Hardware Accelerator for DNN
Conference paper
Tensor-Product-Based Accelerator for Area-efficient and Scalable Number Theoretic Transform
Conference paper
Article
Attack Directories on ARM big.LITTLE Processors
Conference paper
Bayesian Optimization with Clustering and Rollback for CNN Auto Pruning
Conference paper
PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs
Conference paper
Hard-ODT: Hardware-Friendly Online Decision Tree Learning Algorithm and System
Article
AMF-Placer: High-Performance Analytical Mixed-size Placer for FPGA
Conference paper
Energy Efficient In-Memory Integer Multiplication based on Racetrack Memory
Conference paper
Graph Sampling with Fast Random Walker on HBM-enabled FPGA Accelerators
Conference paper
Conference paper
Low Bitwidth CNN Accelerator on FPGA Using Winograd and Block Floating Point Arithmetic
Conference paper
BBB-CFI: Lightweight CFI Approach Against Code-Reuse Attacks Using Basic Block Information
Article
Article
Article
Article
Performance Modeling and Directives Optimization for High Level Synthesis on FPGA
Article
Towards High Performance Low Bitwidth Training for Deep Neural Networks
Article
A history-based auto-tuning framework for fast and high-performance DNN design on GPU
Conference paper
Conference paper
FP-Stereo: Hardware-Efficient Stereo Vision for Embedded Applications
Conference paper
HL-Pow: A Learning-Based Power Modeling Framework for High-Level Synthesis
Conference paper
iGPU Leak: An Information Leakage Vulnerability on Intel Integrated GPU
Conference paper
NCPower: Power Modelling for NVM-based Neuromorphic Chip
Conference paper
Conference paper
An Ensemble Learning Approach for In-Situ Monitoring of FPGA Dynamic Power
Article
A Cost-Effective CNN Accelerator Design with Configurable PU on FPGA
Conference paper
A Hybrid Data-Consistent Framework for Link-Aware AccessManagement in Emerging CPU-FPGA Platforms
Conference paper
Accelerate pattern recognition for cyber security analysis
Conference paper
Hi-clockflow: Multi-clock dataflow automation and throughput optimization in high-level synthesis
Conference paper
LAMA: Link-aware hybrid management for memory accesses in emerging CPU-FPGA platforms
Conference paper
Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis
Conference paper
Poly: Efficient Heterogeneous System and Application Management for Interactive Applications
Conference paper
SGXlinger: A New Side-channel Attack Vector Based on Interrupt Latency against Enclave Execution
Conference paper
Towards Efficient and Scalable Acceleration of Online Decision Tree Learning on FPGA
Conference paper
FIexCL: A Model of Performance and Power for OpenCL Workloads on FPGAs
Article
Hi-DMM: high-performance dynamic memory management in high-level synthesis
Article
Parallelizing Hardware Tasks on Multicontext FPGA With Efficient Placement and Scheduling Algorithms
Article
ROPSentry: Runtime Defense Against ROP Attacks Using Hardware Performance Counters
Article
Article
A collaborative framework for FPGA-based CNN design modeling and optimization
Conference paper
CAMAS: Static and Dynamic Hybrid Cache Management for CPU-FPGA Platforms
Conference paper
Article
A Hybrid Logic Block Architecture in FPGA for Holistic Efficiency
Article
A Variation-Aware Adaptive Fuzzy Control System for Thermal Management of Microprocessors
Article
Fracturable DSP Block for Multi-context Reconfigurable Architectures
Article
HeteroSim: A Heterogeneous CPU-FPGA Simulator
Article
Multikernel Data Partitioning With Channel on OpenCL-Based FPGAs
Article
Pipeline Reconfigurable DSP for Dynamically Reconfigurable Architectures
Article
Scalable Light-Weight Integration of FPGA Based Accelerators with Chip Multi-Processors
Article
Article
In-place logic obfuscation for emerging nonvolatile FPGAs
Book chapter
A Hybrid Approach to Cache Management in Heterogeneous CPU-FPGA Platforms
Conference paper
A Novel Two-stage Modular Multiplier Based on Racetrack Memory for Asymmetric Cryptography
Conference paper
COMBA: A Comprehensive Model-based Analysis Framework for High Level Synthesis of Real Applications
Conference paper
Decision tree based hardware power monitoring for run time dynamic power management in FPGA
Conference paper
Dynamic Module Partitioning for Library Based Placement on Heterogeneous FPGAs
Conference paper
FlexCL: An Analytical Performance Model for OpenCL Workloads on Flexible FPGAs
Conference paper
Conference paper
No-Jump-into-Basic-Block: Enforce Basic Block CFI on the Fly for Real-world Binaries
Conference paper
PAAS: A System Level Simulator For Heterogeneous Computing Architectures
Conference paper
Conference paper
Conference paper
A Fine-Grained Control Flow Integrity Approach Against Runtime Memory Attacks for Embedded Systems
Article
Article
Decentralized Thermal-Aware Task Scheduling for Large-Scale Many-Core Systems
Article
Article
Library-Based Placement and Routing in FPGAs with Support of Partial Reconfiguration
Article
Low-Power FPGA Design Using Memoization-Based Approximate Computing
Article
Melia: A MapReduce Framework on OpenCL-Based FPGAs
Article
Semantics-Based Online Malware Detection: Towards Efficient Real-Time Protection Against Malware
Article
Thermal-Aware Task Scheduling for 3D-Network-on-Chip: A Bottom to Top Scheme
Article
A Discrete Thermal Controller for Chip-Multiprocessors
Conference paper
A Performance Analysis Framework for Optimizing OpenCL Applications on FPGAs
Conference paper
A Racetrack Memory Based In-memory Booth Multiplier for Cryptography Application
Conference paper
Analytical Delay Model for CPU-FPGA Data Paths in Programmable System-on-Chip FPGA
Conference paper
Area Efficient Hardware Architecture for Implicitly Defined Complex Events Processing
Conference paper
HeteroSim: A Heterogeneous CPU-FPGA Simulator
Conference paper
Modular Placement for Interposer based Multi-FPGA Systems
Conference paper
Online Malware Defense Using Attack Behavior Model
Conference paper
Relational Query Processing on OpenCL-based FPGAs
Conference paper
Article
Electro-kinetic phenomena in porous PET films filled with liquid crystals
Article
FDR 2.0: A Low-power Dynamically Reconfigurable Architecture and its FinFET Implementation
Article
Leveraging Hotspots and Improving Chip Reliability via Carbon Nanotube Grid Thermal Structure
Article
A Study of Data Partitioning on OpenCL-based FPGAS
Conference paper
Conference paper
Hierarchical library based power estimator for versatile FPGAs
Conference paper
Hierarchical Library Based Power Estimator for Versatile FPGAs
Conference paper
Improving Data Partitioning Performance on OpenCL-based FPGAS
Conference paper
Static hardware task placement on multi-context FPGA using hybrid genetic algorithm
Conference paper
SynDFG: Synthetic Dataflow Graph Generator for High-level Synthesis
Conference paper
Thermal-aware Task Scheduling for 3D-Network-on-Chip: A bottom-to-Top Scheme
Conference paper
Traffic-aware Application Mapping for Network-on-chip Based Multiprocessor System-on-chip
Conference paper
Two-Photon Excited Fluorescence Emission from Hemoglobin
Conference paper
A fine-grain dynamically reconfigurable architecture aimed at reducing the FPGA-ASIC gaps
Article
Nonvolatile CBRAM-crossbar-based 3-D-integrated hybrid memory for data retention
Article
Systematic Analysis of Crosstalk Noise in Folded-Torus-Based Optical Networks-on-Chip
Article
A low cost acceleration method for hardware trojan detection based on fan-out cone analysis
Conference paper
A low-power pipelined MAC architecture using Baugh-Wooley based multiplier
Conference paper
An extended framework for worst-case throughput analysis with router constraint
Conference paper
FPGA Based Control Flow Checking
Conference paper
Hierarchical Library-Based Power Estimator for Versatile FPGAs
Conference paper
Reconfigurable DSP block design for dynamically reconfigurable architecture
Conference paper
Reconfigurable Dynamic Trusted Platform Module for Control Flow Checking
Conference paper
Reconfigurable Dynamic Trusted Platform Module for Runtime Execution Monitoring
Conference paper
Soft Error Mitigation Through Selection of Non-invert Implication Paths
Conference paper
Sum of products: Computation using modular thermometer codes
Conference paper
Conference paper
Towards Automatic Partial Reconfiguration in FPGAs
Conference paper
A New RNS based DA Approach For Inner Product Computation
Article
Formal Worst-Case Analysis of Crosstalk Noise in Mesh-Based Optical Networks-on-Chip
Article
NBTI Aware Circuit Node Criticality Computation
Article
A Hardware Security Scheme for RRAM-based FPGA
Conference paper
A Network-on-Chip Benchmark Suite Based on Real Applications
Conference paper
Conference paper
Conference paper
Conference paper
Article
A Physical Design Tool for Carbon Nanotube Field-Effect Transistor Circuits
Article
Design Exploration of Hybrid CMOS and Memristor Circuit by New Modified Nodal Analysis
Article
SRAM-based NATURE: A synamically reconfigurable FPGA based on 10T low-power SRAMs
Article
The 3D Stacking Bipolar RRAM for High Density
Article
FONoC: a Fat Tree Based Optical Network-on-Chip for Multiprocessor System-on-Chip
Book chapter
A Look Up Table Design with 3D Bipolar RRAMs
Conference paper
A novel low-waveguide-crossing floorplan for fat tree based optical networks-on-chip
Conference paper
A novel peripheral circuit for RRAM-based LUT
Conference paper
A RRAM-based Memory System and Applications
Conference paper
Conference paper
An Efficient Soft Error Protection Scheme for MPSoC and FPGA-based Verification
Conference paper
Decentralized Agent Based Re-Clustering for Task Mapping of Tera-Scale Network-on-Chip System
Conference paper
Design of low power 3D hybrid memory by non-volatile CBRAM-crossbar with block-level data-retention
Conference paper
Distributed Thermal-Aware Task Scheduling for 3D Network-on-Chip
Conference paper
Fine-grained Dynamic Voltage Scaling on OLED Display
Conference paper
Holistic comparison of optical routers for chip multiprocessors
Conference paper
Non-volatile 3D stacking RRAM-based FPGA
Conference paper
Thermal analysis for 3D optical network-on-chip based on a novel low-cost 6x6 optical router
Conference paper
uBRAM-based Run-time Reconfigurable FPGA and Corresponding Reconfiguration Methodology
Conference paper
Coroutine-based synthesis of efficient embedded software from SystemC models
Article
SRAM-based NATURE: A Dynamically Reconfigurable FPGA Based on 10T Low-power SRAMs
Article
A Hybrid Nano/CMOS Dynamically Reconfigurable System
Book chapter
Book chapter
3D-HIM: A 3D High-density interleaved memory for bipolar RRAM design
Conference paper
A NoC traffic suite based on real applications
Conference paper
An HQV-approved edge directed interpolation algorithm for de-interlacing
Conference paper
Conference paper
Modeling and Analysis of Thermal Effects in Optical Networks-on-Chip
Conference paper
NEMS based Thermal Management for 3D Many-core System
Conference paper
Low-Power 3D Nano/CMOS Hybrid Dynamically Reconfigurable Architecture
Article
A hardware-software collaborated method for soft-error tolerant MPSoC
Conference paper
A Hierarchical Hybrid Optical-Electronic Network-on-Chip
Conference paper
A Unified Inter/Intra-chip Optical Interconnect Network
Conference paper
Crosstalk noise and bit error rate analysis for optical network-on-chip
Conference paper
UNION: A Unified Inter/Intra-Chip Optical Network for chip multiprocessors
Conference paper
A Hybrid Nano/CMOS Dynamically Reconfigurable System – Part I: Architecture
Article
A Hybrid Nano/CMOS Dynamically Reconfigurable System – Part II: Design Optimization Flow
Article
Article
Double-Data-Rate, Wave-Pipelined Interconnect for Asynchronous NoCs
Article
A low-power fat tree-based optical Network-On-Chip for multiprocessor system-on-chip
Conference paper
A Low-power Low-cost Optical Router for Optical Networks-on-Chip in Multiprocessor Systems-on-Chip
Conference paper
Design ASNoC for Low-Power SoCs
Conference paper
Conference paper
NATURE: A Hybrid Nanotube/CMOS Dynamically Reconfigurable Architecture
Conference paper
6 nm half-pitch lines and 0.04 νm 2 static random access memory patterns by nanoimprint lithography
Article
Electrostatic force-assisted nanoimprint lithography
Article
High-performance nanowire-grid polarizers
Article
ALLCN: An Automatic Logic-to-Layout Tool for Carbon Nanotube Based Nanotechnology
Conference paper
Fabrication of 60-nm transistors on 4-in. wafer using nanoimprint at all lithography levels
Article
Pattern transfer fidelity of nanoimprint lithography on six-inch wafers
Article
Electrically Tunable Free-Space Sub-Wavelength Grating Filters with 30nm Tuning Range
Conference paper
Precision nano-optical waveplates
Conference paper
Application of Optimization Methods to Crack Profile Inversion Using Eddy-Current Data
Conference paper
Boosting the Convergence of Reinforcement Learning-based Auto-pruning Using Historical Data
Data-Pattern-Based Predictive On-Chip Power Meter in DNN Accelerator
Deep Reinforcement Learning-Based Power Management for Chiplet-Based Multicore Systems
Unveiling the Advantages of Full Coherency Architecture for FPSoC Systems
A Modular Branch Predictor Performance Analysis Framework for Fast Design Space Exploration
Collaborative Coalescing of Redundant Memory Access for GPU System
DeepIC3: Guiding IC3 Algorithms by Graph Neural Network Clause Prediction
Designing and Accelerating Spiking Neural Network Based on High-Level Synthesis
GraFlex: Flexible Graph Processing on FPGAs through Customized Scalable Interconnection Network
PC-oriented Prediction-based Runtime Power Management for GPGPU using Knowledge Transfer
PhotonNTT: Energy-efficient Parallel Photonic Number Theoretic Transform Accelerator
SCNoCs: An Adaptive Heterogeneous Multi-NoC with Selective Compression and Power Gating
Accelerating Loop-Oriented RTL Simulation with Code Instrumentation
HL-Pow: Learning-Assisted Pre-RTL Power Modeling and Optimization for FPGA HLS
Optimizing for In-Memory Deep Learning With Emerging Memory Technology
ACGraph: Accelerating Streaming Graph Processing via Dependence Hierarchy
Area-efficient and Scalable Accelerator for Number Theoretic Transform Modelled on Tensor Products
Cache Side-channel Attacks and Defenses of the Sliding Window Algorithm in TEEs
DiffLo: A Graph-based Method for Functional Discrepancy Localization in High-level Synthesis.
FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAs
PertNAS: Architectural Perturbations for Memory-Efficient Neural Architecture Search
PROPHET: Predictive On-Chip Power Meter in Hardware Accelerator for DNN
Tensor-Product-Based Accelerator for Area-efficient and Scalable Number Theoretic Transform
AMF-Placer: High-Performance Analytical Mixed-size Placer for FPGA
Energy Efficient In-Memory Integer Multiplication based on Racetrack Memory
Graph Sampling with Fast Random Walker on HBM-enabled FPGA Accelerators
Low Bitwidth CNN Accelerator on FPGA Using Winograd and Block Floating Point Arithmetic
BBB-CFI: Lightweight CFI Approach Against Code-Reuse Attacks Using Basic Block Information
Performance Modeling and Directives Optimization for High Level Synthesis on FPGA
Towards High Performance Low Bitwidth Training for Deep Neural Networks
A history-based auto-tuning framework for fast and high-performance DNN design on GPU
FP-Stereo: Hardware-Efficient Stereo Vision for Embedded Applications
HL-Pow: A Learning-Based Power Modeling Framework for High-Level Synthesis
iGPU Leak: An Information Leakage Vulnerability on Intel Integrated GPU
A Cost-Effective CNN Accelerator Design with Configurable PU on FPGA
A Hybrid Data-Consistent Framework for Link-Aware AccessManagement in Emerging CPU-FPGA Platforms
Hi-clockflow: Multi-clock dataflow automation and throughput optimization in high-level synthesis
LAMA: Link-aware hybrid management for memory accesses in emerging CPU-FPGA platforms
Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis
Poly: Efficient Heterogeneous System and Application Management for Interactive Applications
SGXlinger: A New Side-channel Attack Vector Based on Interrupt Latency against Enclave Execution
Towards Efficient and Scalable Acceleration of Online Decision Tree Learning on FPGA
FIexCL: A Model of Performance and Power for OpenCL Workloads on FPGAs
Hi-DMM: high-performance dynamic memory management in high-level synthesis
Parallelizing Hardware Tasks on Multicontext FPGA With Efficient Placement and Scheduling Algorithms
ROPSentry: Runtime Defense Against ROP Attacks Using Hardware Performance Counters
A Hybrid Logic Block Architecture in FPGA for Holistic Efficiency
A Variation-Aware Adaptive Fuzzy Control System for Thermal Management of Microprocessors
Fracturable DSP Block for Multi-context Reconfigurable Architectures
Multikernel Data Partitioning With Channel on OpenCL-Based FPGAs
Pipeline Reconfigurable DSP for Dynamically Reconfigurable Architectures
Scalable Light-Weight Integration of FPGA Based Accelerators with Chip Multi-Processors
A Hybrid Approach to Cache Management in Heterogeneous CPU-FPGA Platforms
A Novel Two-stage Modular Multiplier Based on Racetrack Memory for Asymmetric Cryptography
COMBA: A Comprehensive Model-based Analysis Framework for High Level Synthesis of Real Applications
Decision tree based hardware power monitoring for run time dynamic power management in FPGA
Dynamic Module Partitioning for Library Based Placement on Heterogeneous FPGAs
FlexCL: An Analytical Performance Model for OpenCL Workloads on Flexible FPGAs
No-Jump-into-Basic-Block: Enforce Basic Block CFI on the Fly for Real-world Binaries
PAAS: A System Level Simulator For Heterogeneous Computing Architectures
A Fine-Grained Control Flow Integrity Approach Against Runtime Memory Attacks for Embedded Systems
Decentralized Thermal-Aware Task Scheduling for Large-Scale Many-Core Systems
Library-Based Placement and Routing in FPGAs with Support of Partial Reconfiguration
Low-Power FPGA Design Using Memoization-Based Approximate Computing
Semantics-Based Online Malware Detection: Towards Efficient Real-Time Protection Against Malware
Thermal-Aware Task Scheduling for 3D-Network-on-Chip: A Bottom to Top Scheme
A Performance Analysis Framework for Optimizing OpenCL Applications on FPGAs
A Racetrack Memory Based In-memory Booth Multiplier for Cryptography Application
Analytical Delay Model for CPU-FPGA Data Paths in Programmable System-on-Chip FPGA
Area Efficient Hardware Architecture for Implicitly Defined Complex Events Processing
Electro-kinetic phenomena in porous PET films filled with liquid crystals
FDR 2.0: A Low-power Dynamically Reconfigurable Architecture and its FinFET Implementation
Leveraging Hotspots and Improving Chip Reliability via Carbon Nanotube Grid Thermal Structure
Hierarchical library based power estimator for versatile FPGAs
Hierarchical Library Based Power Estimator for Versatile FPGAs
Improving Data Partitioning Performance on OpenCL-based FPGAS
Static hardware task placement on multi-context FPGA using hybrid genetic algorithm
SynDFG: Synthetic Dataflow Graph Generator for High-level Synthesis
Thermal-aware Task Scheduling for 3D-Network-on-Chip: A bottom-to-Top Scheme
Traffic-aware Application Mapping for Network-on-chip Based Multiprocessor System-on-chip
A fine-grain dynamically reconfigurable architecture aimed at reducing the FPGA-ASIC gaps
Nonvolatile CBRAM-crossbar-based 3-D-integrated hybrid memory for data retention
Systematic Analysis of Crosstalk Noise in Folded-Torus-Based Optical Networks-on-Chip
A low cost acceleration method for hardware trojan detection based on fan-out cone analysis
A low-power pipelined MAC architecture using Baugh-Wooley based multiplier
An extended framework for worst-case throughput analysis with router constraint
Hierarchical Library-Based Power Estimator for Versatile FPGAs
Reconfigurable DSP block design for dynamically reconfigurable architecture
Reconfigurable Dynamic Trusted Platform Module for Control Flow Checking
Reconfigurable Dynamic Trusted Platform Module for Runtime Execution Monitoring
Soft Error Mitigation Through Selection of Non-invert Implication Paths
Sum of products: Computation using modular thermometer codes
A Physical Design Tool for Carbon Nanotube Field-Effect Transistor Circuits
Design Exploration of Hybrid CMOS and Memristor Circuit by New Modified Nodal Analysis
SRAM-based NATURE: A synamically reconfigurable FPGA based on 10T low-power SRAMs
A novel low-waveguide-crossing floorplan for fat tree based optical networks-on-chip
An Efficient Soft Error Protection Scheme for MPSoC and FPGA-based Verification
Decentralized Agent Based Re-Clustering for Task Mapping of Tera-Scale Network-on-Chip System
Design of low power 3D hybrid memory by non-volatile CBRAM-crossbar with block-level data-retention
Distributed Thermal-Aware Task Scheduling for 3D Network-on-Chip
Holistic comparison of optical routers for chip multiprocessors
Thermal analysis for 3D optical network-on-chip based on a novel low-cost 6x6 optical router
uBRAM-based Run-time Reconfigurable FPGA and Corresponding Reconfiguration Methodology
Coroutine-based synthesis of efficient embedded software from SystemC models
SRAM-based NATURE: A Dynamically Reconfigurable FPGA Based on 10T Low-power SRAMs
NATURE: A Hybrid Nanotube/CMOS Dynamically Reconfigurable Architecture
FIexCL: A Model of Performance and Power for OpenCL Workloads on FPGAs
Article
Hi-DMM: high-performance dynamic memory management in high-level synthesis
Article
Parallelizing Hardware Tasks on Multicontext FPGA With Efficient Placement and Scheduling Algorithms
Article
ROPSentry: Runtime Defense Against ROP Attacks Using Hardware Performance Counters
Article
Article
A collaborative framework for FPGA-based CNN design modeling and optimization
Conference paper
CAMAS: Static and Dynamic Hybrid Cache Management for CPU-FPGA Platforms
Conference paper
Article
A Hybrid Logic Block Architecture in FPGA for Holistic Efficiency
Article
A Variation-Aware Adaptive Fuzzy Control System for Thermal Management of Microprocessors
Article
Fracturable DSP Block for Multi-context Reconfigurable Architectures
Article
HeteroSim: A Heterogeneous CPU-FPGA Simulator
Article
Multikernel Data Partitioning With Channel on OpenCL-Based FPGAs
Article
Pipeline Reconfigurable DSP for Dynamically Reconfigurable Architectures
Article
Scalable Light-Weight Integration of FPGA Based Accelerators with Chip Multi-Processors
Article
Article
In-place logic obfuscation for emerging nonvolatile FPGAs
Book chapter
A Hybrid Approach to Cache Management in Heterogeneous CPU-FPGA Platforms
Conference paper
A Novel Two-stage Modular Multiplier Based on Racetrack Memory for Asymmetric Cryptography
Conference paper
COMBA: A Comprehensive Model-based Analysis Framework for High Level Synthesis of Real Applications
Conference paper
Decision tree based hardware power monitoring for run time dynamic power management in FPGA
Conference paper
Dynamic Module Partitioning for Library Based Placement on Heterogeneous FPGAs
Conference paper
FlexCL: An Analytical Performance Model for OpenCL Workloads on Flexible FPGAs
Conference paper
Conference paper
No-Jump-into-Basic-Block: Enforce Basic Block CFI on the Fly for Real-world Binaries
Conference paper
PAAS: A System Level Simulator For Heterogeneous Computing Architectures
Conference paper
Conference paper
Conference paper
A Fine-Grained Control Flow Integrity Approach Against Runtime Memory Attacks for Embedded Systems
Article
Article
Decentralized Thermal-Aware Task Scheduling for Large-Scale Many-Core Systems
Article
Article
Library-Based Placement and Routing in FPGAs with Support of Partial Reconfiguration
Article
Low-Power FPGA Design Using Memoization-Based Approximate Computing
Article
Melia: A MapReduce Framework on OpenCL-Based FPGAs
Article
Semantics-Based Online Malware Detection: Towards Efficient Real-Time Protection Against Malware
Article
Thermal-Aware Task Scheduling for 3D-Network-on-Chip: A Bottom to Top Scheme
Article
A Discrete Thermal Controller for Chip-Multiprocessors
Conference paper
A Performance Analysis Framework for Optimizing OpenCL Applications on FPGAs
Conference paper
A Racetrack Memory Based In-memory Booth Multiplier for Cryptography Application
Conference paper
Analytical Delay Model for CPU-FPGA Data Paths in Programmable System-on-Chip FPGA
Conference paper
Area Efficient Hardware Architecture for Implicitly Defined Complex Events Processing
Conference paper
HeteroSim: A Heterogeneous CPU-FPGA Simulator
Conference paper
Modular Placement for Interposer based Multi-FPGA Systems
Conference paper
Online Malware Defense Using Attack Behavior Model
Conference paper
Relational Query Processing on OpenCL-based FPGAs
Conference paper
Article
Electro-kinetic phenomena in porous PET films filled with liquid crystals
Article
FDR 2.0: A Low-power Dynamically Reconfigurable Architecture and its FinFET Implementation
Article
Leveraging Hotspots and Improving Chip Reliability via Carbon Nanotube Grid Thermal Structure
Article
A Study of Data Partitioning on OpenCL-based FPGAS
Conference paper
Conference paper
Hierarchical library based power estimator for versatile FPGAs
Conference paper
Hierarchical Library Based Power Estimator for Versatile FPGAs
Conference paper
Improving Data Partitioning Performance on OpenCL-based FPGAS
Conference paper
Static hardware task placement on multi-context FPGA using hybrid genetic algorithm
Conference paper
SynDFG: Synthetic Dataflow Graph Generator for High-level Synthesis
Conference paper
Thermal-aware Task Scheduling for 3D-Network-on-Chip: A bottom-to-Top Scheme
Conference paper
Traffic-aware Application Mapping for Network-on-chip Based Multiprocessor System-on-chip
Conference paper
Two-Photon Excited Fluorescence Emission from Hemoglobin
Conference paper
A fine-grain dynamically reconfigurable architecture aimed at reducing the FPGA-ASIC gaps
Article
Nonvolatile CBRAM-crossbar-based 3-D-integrated hybrid memory for data retention
Article
Systematic Analysis of Crosstalk Noise in Folded-Torus-Based Optical Networks-on-Chip
Article
A low cost acceleration method for hardware trojan detection based on fan-out cone analysis
Conference paper
A low-power pipelined MAC architecture using Baugh-Wooley based multiplier
Conference paper
An extended framework for worst-case throughput analysis with router constraint
Conference paper
FPGA Based Control Flow Checking
Conference paper
Hierarchical Library-Based Power Estimator for Versatile FPGAs
Conference paper
Reconfigurable DSP block design for dynamically reconfigurable architecture
Conference paper
Reconfigurable Dynamic Trusted Platform Module for Control Flow Checking
Conference paper
Reconfigurable Dynamic Trusted Platform Module for Runtime Execution Monitoring
Conference paper
Soft Error Mitigation Through Selection of Non-invert Implication Paths
Conference paper
Sum of products: Computation using modular thermometer codes
Conference paper
Conference paper
Towards Automatic Partial Reconfiguration in FPGAs
Conference paper
A New RNS based DA Approach For Inner Product Computation
Article
Formal Worst-Case Analysis of Crosstalk Noise in Mesh-Based Optical Networks-on-Chip
Article
NBTI Aware Circuit Node Criticality Computation
Article
A Hardware Security Scheme for RRAM-based FPGA
Conference paper
A Network-on-Chip Benchmark Suite Based on Real Applications
Conference paper
Conference paper
Conference paper
Conference paper
Article
A Physical Design Tool for Carbon Nanotube Field-Effect Transistor Circuits
Article
Design Exploration of Hybrid CMOS and Memristor Circuit by New Modified Nodal Analysis
Article
SRAM-based NATURE: A synamically reconfigurable FPGA based on 10T low-power SRAMs
Article
The 3D Stacking Bipolar RRAM for High Density
Article
FONoC: a Fat Tree Based Optical Network-on-Chip for Multiprocessor System-on-Chip
Book chapter
A Look Up Table Design with 3D Bipolar RRAMs
Conference paper
A novel low-waveguide-crossing floorplan for fat tree based optical networks-on-chip
Conference paper
A novel peripheral circuit for RRAM-based LUT
Conference paper
A RRAM-based Memory System and Applications
Conference paper
Conference paper
An Efficient Soft Error Protection Scheme for MPSoC and FPGA-based Verification
Conference paper
Decentralized Agent Based Re-Clustering for Task Mapping of Tera-Scale Network-on-Chip System
Conference paper
Design of low power 3D hybrid memory by non-volatile CBRAM-crossbar with block-level data-retention
Conference paper
Distributed Thermal-Aware Task Scheduling for 3D Network-on-Chip
Conference paper
Fine-grained Dynamic Voltage Scaling on OLED Display
Conference paper
Holistic comparison of optical routers for chip multiprocessors
Conference paper
Non-volatile 3D stacking RRAM-based FPGA
Conference paper
Thermal analysis for 3D optical network-on-chip based on a novel low-cost 6x6 optical router
Conference paper
uBRAM-based Run-time Reconfigurable FPGA and Corresponding Reconfiguration Methodology
Conference paper
Coroutine-based synthesis of efficient embedded software from SystemC models
Article
SRAM-based NATURE: A Dynamically Reconfigurable FPGA Based on 10T Low-power SRAMs
Article
A Hybrid Nano/CMOS Dynamically Reconfigurable System
Book chapter
Book chapter
3D-HIM: A 3D High-density interleaved memory for bipolar RRAM design
Conference paper
A NoC traffic suite based on real applications
Conference paper
An HQV-approved edge directed interpolation algorithm for de-interlacing
Conference paper
Conference paper
Modeling and Analysis of Thermal Effects in Optical Networks-on-Chip
Conference paper
NEMS based Thermal Management for 3D Many-core System
Conference paper
Low-Power 3D Nano/CMOS Hybrid Dynamically Reconfigurable Architecture
Article
A hardware-software collaborated method for soft-error tolerant MPSoC
Conference paper
A Hierarchical Hybrid Optical-Electronic Network-on-Chip
Conference paper
A Unified Inter/Intra-chip Optical Interconnect Network
Conference paper
Crosstalk noise and bit error rate analysis for optical network-on-chip
Conference paper
UNION: A Unified Inter/Intra-Chip Optical Network for chip multiprocessors
Conference paper
A Hybrid Nano/CMOS Dynamically Reconfigurable System – Part I: Architecture
Article
A Hybrid Nano/CMOS Dynamically Reconfigurable System – Part II: Design Optimization Flow
Article
Article
Double-Data-Rate, Wave-Pipelined Interconnect for Asynchronous NoCs
Article
A low-power fat tree-based optical Network-On-Chip for multiprocessor system-on-chip
Conference paper
A Low-power Low-cost Optical Router for Optical Networks-on-Chip in Multiprocessor Systems-on-Chip
Conference paper
Design ASNoC for Low-Power SoCs
Conference paper
Conference paper
NATURE: A Hybrid Nanotube/CMOS Dynamically Reconfigurable Architecture
Conference paper
6 nm half-pitch lines and 0.04 νm 2 static random access memory patterns by nanoimprint lithography
Article
Electrostatic force-assisted nanoimprint lithography
Article
High-performance nanowire-grid polarizers
Article
ALLCN: An Automatic Logic-to-Layout Tool for Carbon Nanotube Based Nanotechnology
Conference paper
Fabrication of 60-nm transistors on 4-in. wafer using nanoimprint at all lithography levels
Article
Pattern transfer fidelity of nanoimprint lithography on six-inch wafers
Article
Electrically Tunable Free-Space Sub-Wavelength Grating Filters with 30nm Tuning Range
Conference paper
Precision nano-optical waveplates
Conference paper
Application of Optimization Methods to Crack Profile Inversion Using Eddy-Current Data
Conference paper
EESM5060 | Embedded Systems |
ELEC4320 | FPGA-based Design: From Theory to Practice |
CPEG4911 | Computer Engineering Final Year Project in ELEC |
ELEC4900 | Final Year Design Project |
ELEC4940C | Independent Study |
ELEC5140 | Advanced Computer Architecture |
EESM5060 | Embedded Systems |
ELEC4320 | FPGA-based Design: From Theory to Practice |
No Teaching Assignments |
No Teaching Assignments |
No Teaching Assignments |
CHEN, Lin
(co-supervision)
Electronic and Computer Engineering
JIANG, Jingbo
Electronic and Computer Engineering
LI, Shangkun
Electronic and Computer Engineering
LI, Wenkai
(co-supervision)
Electronic and Computer Engineering
LI, Zeyu
Electronic and Computer Engineering
LIANG, Jiawei
Electronic and Computer Engineering
LIU, Xingyu
Electronic and Computer Engineering
LIU, Yinyi
(co-supervision)
Electronic and Computer Engineering
SHAO, Jiaqi
Electronic and Computer Engineering
WU, Jin
Electronic and Computer Engineering
CHEN, Ruisi
Electronic and Computer Engineering
FAN, Hanwei
Electronic and Computer Engineering
MA, Chaofang
Electronic and Computer Engineering
SATHI, Sarveswara Reddy
Electronic and Computer Engineering
ZHANG, Yipu
Electronic and Computer Engineering
CHEN, Liangji
Individualized Interdisciplinary Program (Microelectronics)
DU, Linfeng
Electronic and Computer Engineering
HU, Guangyu
(co-supervision)
Individualized Interdisciplinary Program (Microelectronics)
PENG, Jian
Electronic and Computer Engineering
SUN, Ge
(co-supervision)
Individualized Interdisciplinary Program (Robotics and Autonomous Systems)
WANG, Ya
Electronic and Computer Engineering
ZHOU, Zhongchun
Electronic and Computer Engineering
LAI, Chengtao
Electronic and Computer Engineering
ZHANG, Yuying
Electronic and Computer Engineering
ZHOU, Xiaofeng
Electronic and Computer Engineering
AHMAD, Afzal
Electronic and Computer Engineering
LI, Enlai
Electronic and Computer Engineering
ZHONG, Shuai
Electronic and Computer Engineering
SU, Chunyou
Electronic and Computer Engineering
TAHGHIGHI, Mohammad
Electronic and Computer Engineering
LUK, Pak Him
Electronic and Computer Engineering
GE, Jinming
Electronic and Computer Engineering
MA, Haoxuan
Electronic and Computer Engineering
CHEN, Shixi
(co-supervision)
Electronic and Computer Engineering( Completed in 2024 )
JIANG, Fan
(co-supervision)
Electronic and Computer Engineering( Completed in 2024 )
KOU, Zili
Electronic and Computer Engineering( Completed in 2024 )
LI, Chengeng
(co-supervision)
Electronic and Computer Engineering( Completed in 2024 )
ZHANG, Jiaxu
(co-supervision)
Electronic and Computer Engineering( Completed in 2024 )
LI, Xiao
(co-supervision)
Electronic and Computer Engineering( Completed in 2023 )
LIANG, Tingyuan
Electronic and Computer Engineering( Completed in 2022 )
MU, Jiandong
Electronic and Computer Engineering( Completed in 2021 )
YANG, Hao
Electronic and Computer Engineering( Completed in 2024 )
FAN, Hanwei
(co-supervision)
Individualized Interdisciplinary Program (Microelectronics)( Completed in 2023 )
SHI, Xu
Electronic and Computer Engineering( Completed in 2023 )
ZHENG, Yile
Electronic and Computer Engineering( Completed in 2023 )
DU, Linfeng
Electronic and Computer Engineering( Completed in 2022 )
PENG, Jian
Electronic and Computer Engineering( Completed in 2022 )
SATHI, Sarveswara Reddy
Electronic and Computer Engineering( Completed in 2022 )
ZHANG, Qingwen
(co-supervision)
Individualized Interdisciplinary Program (Robotics and Autonomous Systems)( Completed in 2022 )
WONG, Yuk
Electronic and Computer Engineering( Completed in 2021 )
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