Labeled-to-unlabeled distribution alignment for partially-supervised multi-organ medical image segmentation

BoNuS: Boundary Mining for Nuclei Segmentation with Partial Point Labels

Deep Learning in Breast Cancer Imaging: A Decade of Progress and Future Directions

DyBit: Dynamic Bit-Precision Numbers for Efficient Quantized Neural Network Inference

Joint stereo 3D object detection and implicit surface reconstruction

LENAS: Learning-Based Neural Architecture Search and Ensemble for 3-D Radiotherapy Dose Prediction

Semantic memory-based dynamic neural network using memristive ternary CIM and CAM for 2D and 3D vision

UCTNet: Uncertainty-guided CNN-Transformer hybrid networks for medical image segmentation

Vessel-promoted OCT to OCTA image translation by heuristic contextual constraints

A Tale of Two Domains: Exploring Efficient Architecture Design for Truly Autonomous Things

AdaP-CIM: Compute-in-Memory Based Neural Network Accelerator using Adaptive Posit

Aligning Medical Images with General Knowledge from Large Language Models

BOLS: A Bionic Sensor-direct On-chip Learning System with Direct-Feedback-Through-Time for Personalized Wearable Health Monitoring

DTMFormer: Dynamic Token Merging for Boosting Transformer-Based Medical Image Segmentation

Iterative Online Image Synthesis via Diffusion Model for Imbalanced Classification

Multi-Issue Butterfly Architecture for Sparse Convex Quadratic Programming

A Tiny Accelerator for Mixed-bit Sparse CNN based on Efficient Fetch Method of SIMO SPad

BATFormer: Towards Boundary-Aware Lightweight Transformer for Efficient Medical Image Segmentation

CAE-GReaT: Convolutional-Auxiliary Efficient Graph Reasoning Transformer for Dense Image Predictions

Compete to Win: Enhancing Pseudo Labels for Barely-supervised Medical Image Segmentation

Cyclical Self-Supervision for Semi-Supervised Ejection Fraction Prediction from Echocardiogram Videos

Dual-distribution discrepancy with self-supervised refinement for anomaly detection in medical images

Dynamic Subcluster-Aware Network for Few-Shot Skin Disease Classification

Echo state graph neural networks with analogue random resistive memory arrays

Exploring Feature Representation Learning for Semi-supervised Medical Image Segmentation

FedMix: Mixed Supervised Federated Learning for Medical Image Segmentation

M² FTrans: Modality-Masked Fusion Transformer for Incomplete Multi-Modality Brain Tumor Segmentation

Nuclei segmentation with point annotations from pathology images via self-supervised learning and co-training

Path-Analysis-Based Reinforcement Learning Algorithm for Imitation Filming

The Lighter The Better: Rethinking Transformers in Medical Image Segmentation Through Adaptive Pruning

A 1920×1080 129fps 4.3pJ/pixel Stereo-Matching Processor for Pico Aerial Vehicles

Architecting Efficient Multi-modal AIoT Systems

AutoDCIM: An Automated Digital CIM Compiler

Automated Vision-Based Wellness Analysis for Elderly Care Centers

Binary is All You Need: Ultra-Efficient Arrhythmia Detection with a Binary-Only Compressive System

BIOS: A 40nm Bionic Sensor-defined 0.47pJ/SOP, 268.7TSOPs/W Configurable Spiking Neuron-in-Memory Processor for Wearable Healthcare

FedIIC: Towards Robust Federated Learning for Class-Imbalanced Medical Image Classification

FedNoRo: Towards Noise-Robust Federated Learning by Addressing Class Imbalance and Label Noise Heterogeneity

Few Shot Medical Image Segmentation with Cross Attention Transformer

FoodWise: Food Waste Reduction and Behavior Change on Campus with Data Visualization and Gamification

LLM-FP4: 4-Bit Floating-Point Quantized Transformers

MMBench: Benchmarking End-to-End Multi-modal DNNs and Understanding Their Hardware-Software Implications

MMExit: Enabling Fast and Efficient Multi-modal DNN Inference with Adaptive Network Exits

NOLS: A Near-sensor On-chip Learning System with Direct Feedback Alignment for Personalized Wearable Heart Health Monitoring

Oscillation-free Quantization for Low-bit Vision Transformers

PIM-HLS: An Automatic Hardware Generation Tool for Heterogeneous Processing-In-Memory-based Neural Network Accelerators

Radiomics-Informed Deep Learning for Classification of Atrial Fibrilation Sub-Types from Left-Atrium CT Volumes

Randomized Quantization: A Generic Augmentation for Data Agnostic Self-supervised Learning

Rethinking Boundary Detection in Deep Learning Models for Medical Image Segmentation

RVComp: Analog Variation Compensation for RRAM-Based in-Memory Computing

Semi-Supervised Contrastive Learning for Deep Regression with Ordinal Rankings from Spectral Seriation

Semi-Supervised Deep Regression with Uncertainty Consistency and Variational Model Ensembling via Bayesian Neural Networks

SMG: A System-Level Modality Gating Facility for Fast and Energy-Efficient Multimodal Computing

SNNOpt: An Application-Specific Design Framework for Spiking Neural Networks

Adaptive Contrast for Image Regression in Computer-Aided Disease Assessment

Characterizing and Understanding End-to-End Multi-Modal Neural Networks on GPUs

Customized Federated Learning for Multi-Source Decentralized Medical Image Classification

HyCA: A Hybrid Computing Architecture for Fault-Tolerant Deep Learning

Imitation Learning-based Algorithm for Drone Cinematography System

One-Shot Imitation Drone Filming of Human Motion Videos

ReAAP: A Reconfigurable and Algorithm-Oriented Array Processor with Compiler-Architecture Co-Design

Data-Free Neural Architecture Search via Recursive Label Calibration

Dual-Distribution Discrepancy for Anomaly Detection in Chest X-Rays

Graph Reasoning Transformer for Image Parsing

InsMix: Towards Realistic Generative Data Augmentation for Nuclei Instance Segmentation

Nonuniform-to-Uniform Quantization: Towards Accurate Quantization via Generalized Straight-Through Estimation

SDQ: Stochastic Differentiable Quantization with Mixed Precision

Stereo Neural Vernier Caliper

Vision Transformer Slimming: Multi-Dimension Searching in Continuous Optimization Space

Energy Efficiency and Yield Optimization for Optical Interconnects via Transceiver Grouping

Fast Depth Prediction and Obstacle Avoidance on a Monocular Drone Using Probabilistic Convolutional Neural Network

Joint Multi-Dimension Pruning via Numerical Gradient Update

R2F: A Remote Retraining Framework For AIoT Processors With Computing Errors

Ratio-based multi-level resistive memory cells

Reliability Evaluation and Analysis of FPGA-Based Neural Network Acceleration System

The 2021 flexible and printed electronics roadmap

Exploring Intermediate Representation for Monocular Vehicle Pose Estimation

High-fidelity and Large-Area Flexible Hybrid Sensing System (Invited)

How do Adam and Training Strategies Help BNNs Optimization?

Is Label Smoothing Truly Incompatible with Knowledge Distillation: An Empirical Study

Partial Is Better Than All: Revisiting Fine-tuning Strategy for Few-shot Learning

S²-BNN: Bridging the Gap Between Self-Supervised Real and 1-Bit Neural Networks via Guided Distribution Calibration

Towards Robust Dual-View Transformation via Densifying Sparse Supervision for Mammography Lesion Matching

Traffic-Adaptive Power Reconfiguration for Energy-Efficient and Energy-Proportional Optical Interconnects

Bi-modality Medical Image Synthesis using Semi-supervised Sequential Generative Adversarial Networks

Bi-Real Net: Binarizing Deep Network Towards Real-Network Performance

Enabling a Single Deep Learning Model for Accurate Gland Instance Segmentation: A Shape-Aware Adversarial Learning Framework

Multi-task Siamese Network for Retinal Artery/Vein Separation via Deep Convolution along Vessel

Process design kit and design automation for flexible hybrid electronics

Roadmap on emerging hardware and technology for machine learning

Semi-supervised mp-MRI Data Synthesis with StitchLayer and Auxiliary Distance Maximization

Variation-Aware Federated Learning with Multi-Source Decentralized Medical Image Data

A Hybrid Computing Architecture for Fault-tolerant Deep Learning Accelerators

Binarizing MobileNet via Evolution-Based Searching

Cascaded Deep Monocular 3D Human Pose Estimation With Evolutionary Training Data

Characterization and applications of spatial variation models for silicon microring-based optical transceivers

Multi-phase and Multi-level Selective Feature Fusion for Automated Pancreas Segmentation from CT Images

Persistent fault analysis of neural networks on FPGA-based acceleration system

ReActNet: Towards Precise Binary Neural Network with Generalized Activation Functions

Robust design of large area flexible electronics via compressed sensing

A Three-stage Deep Learning Model for Accurate Retinal Vessel Segmentation

A Two-Stage Convolutional Neural Network for Pulmonary Embolism Detection From CTPA Images

Bayesian DeNet: Monocular Depth Prediction and Frame-wise Fusion with Synchronized Uncertainty

Compact Modeling of Thin-Film Transistors for Flexible Hybrid IoT Design

Low-voltage High-performance Flexible Digital and Analog Circuits Based on Ultrahigh-purity Semiconducting Carbon Nanotubes

Process Design Kit and Design Automation for Flexible Hybrid Electronics

Reactive obstacle avoidance of monocular quadrotors with online adapted depth prediction network

Real-Time Dense Monocular SLAM With Online Adapted Depth Prediction Network

Real-time Semantic Plane Reconstruction on a Monocular Drone Using Sparse Fusion

Automated Pulmonary Embolism Detection from CTPA Images Using an End-to-End Convolutional Neural Network

Bidirectional tuning of microring-based silicon photonic transceivers for optimal energy efficiency

Evaluating Assertion Set Completeness to Expose Hardware Trojans and Verification Blindspots

Latent weights do not exist: Rethinking binarized neural network optimization

Learning to Capture a Film-Look Video with a Camera Drone

Learning to Film from Professional Human Motion Videos

MetaPruning: Meta Learning for Automatic Neural Network Channel Pruning

Pre-silicon Formal Verification of JTAG Instruction Opcodes for Security

Process design kit and design automation for flexible hybrid electronics

Process Design Kit and Design Automation for Flexible Hybrid Electronics

Process Design Kit and Design Automation for Flexible Hybrid Electronics

Taming Emerging Devices' Variation and Reliability Challenges with Architectural and System Solutions [Invited]

Task mapping-assisted laser power scaling for optical network-on-chips

Ultra-thin Skin Electronics for High Quality and Continuous Skin-Sensor-Silicon Interfacing

Visualizing the Decision-making Process in Deep Neural Decision Forest

A Lightweight Piecewise Linear Synthesis Method for Standard 12-lead ECG Signals Based on Adaptive Region Segmentation

A Skeletal Similarity Metric for Quality Evaluation of Retinal Vessel Segmentation

Accurate Face Alignment and Adaptive Patch Selection for Heart Rate Estimation From Videos Under Realistic Scenarios

Automated Detection of Clinically Significant Prostate Cancer in mp-MRI Images Based on an End-to-End Deep Neural Network

Joint Segment-Level and Pixel-Wise Losses for Deep Learning Based Retinal Vessel Segmentation

Resistive random-access memory based on ratioed memristors

Robust and Real-time Pose Tracking for Augmented Reality on Mobile Devices

A Deep Model with Shape-preserving Loss for Gland Instance Segmentation

ACT: An Autonomous Drone Cinematography System for Action Scenes

Bi-Real Net: Enhancing the Performance of 1-bit CNNs with Improved Representational Capability and Advanced Training Algorithm

Compact Modeling of Carbon Nanotube Thin Film Transistors for Flexible Circuit Design

Energy-Efficient Channel Alignment of DWDM Silicon Photonic Transceivers

Fully Printed Organic Pseudo-CMOS Circuits for Sensing Applications

Monocular Camera Based Real-time Dense Mapping Using Generative Adversarial Network

Pairing of Microring-based Silicon Photonic Transceivers for Tuning Power Optimization

Process Design Kit for Flexible Hybrid Electronics

StitchAD-GAN for Synthesizing Apparent Diffusion Coefficient Images of Clinically Significant Prostate Cancer

Through-the-Lens Drone Filming

A multiply-add engine with monolithically integrated 3D memristor crossbar/CMOS hybrid circuit

An Automated Method for Accurate Vessel Segmentation

Automated Diagnosis of Prostate Cancer in Multi-Parametric MRI Based on Multimodal Convolutional Neural Networks

Compact Modeling for Silicon Photonic Heterogeneously Integrated Circuits

Co-trained Convolutional Neural Networks for Automated Detection of Prostate Cancer in Multi-parametric MRI

Hiding Hardware Trojan Communication Channels in Partially Specified SoC Bus Functionality

Verification and Trust for Unspecified IP Functionality

3D-DPE: A 3D High-Bandwidth Dot-Product Engine for High-Performance Neuromorphic Computing

An Artificial Neural Network Approach for Screening Test Escapes

Compact Modeling and Circuit-Level Simulation of Silicon Nanophotonic Interconnects

Detecting Hardware Trojans in Unspecified Functionality through Solving Satisfiability Problems

DLPS: Dynamic Laser Power Scaling for Optical Network-on-Chip

Joint Detection and Diagnosis of Prostate Cancer in Multi-parametric MRI Based on Multimodal Convolutional Neural Networks

Mining Mutation Testing Simulation Traces for Security and Testbench Debugging

REDBEE: A visual-inertial drone system for real-time moving object detection

Robust Design and Design Automation for Flexible Hybrid Electronics

An Efficient Network-on-Chip Yield Estimation Approach Based on Gibbs Sampling

Associative Memristive Memory for Approximate Computing in GPUs

Renal Compartment Segmentation in DCE-MRI Images

Automatic Test Pattern Generation

A Low-Power Hybrid Reconfigurable Architecture For Resistive Random-Access Memories

A Wearable Signal Acquisition System for Physiological Signs Including Throat PPG

Accurate and Efficient Pulse Measurement from Facial Videos on Smartphones

Detecting Hardware Trojans in Unspecified Functionality Using Mutation Testing

Hardware Trojans in Incompletely Specified On-chip Bus Systems

In-place Repair for Resistive Memories Utilizing Complementary Resistive Switches

Large-Signal Model for Small-Size High-Speed Carrier-Injection Silicon Microring Modulator

Local Feature Descriptor Learning with Adaptive Siamese Network

OGB: A Distinctive and Efficient Feature for Mobile Augmented Reality

Pairwise Proximity-Based Features for Test Escape Screening

Printed Circuits on Flexible Substrates: Opportunities and Challenges (invited paper)

Process-variation tolerant flexible circuit for wearable electronics

Spatial Pattern Analysis of Process Variations in Silicon Microring Modulators

Trojans Modifying Soft-Processor Instruction Sequences Embedded in FPGA Bitstreams

Variation and Failure Characterization Through Pattern Classification of Test Data From Multiple Test Stages

A low-Power Variation-Aware Adaptive Write Scheme for Access-Transistor-Free Memristive Memory

A Power Efficient Test Data Compression Method on Count Compatible PRL Coding

Athermal silicon ring resonators clad with titanium dioxide for 1.3µm wavelength operation

Compact models for carrier-injection silicon microring modulators

Design, Automation, and Test for Low-Power and Reliable Flexible Electronics

Mobile Image Search: Challenges and Methods

[POSTER] Fusion of Vision and Inertial Sensing for Accurate and Efficient Pose Tracking on Smartphones

20 Gb/s Carrier-Injection Silicon Microring Modulator with SPICE-Compatible Dynamic Model

A Configurable CMOS Memory Platform for 3D-Integrated Memristors

Accurate Vessel Segmentation with Progressive Contrast Enhancement and Canny Refinement

AdaTest: An Efficient Statistical Test Framework for Test Escape Screening

Approximate Associative Memristive Memory for Energy-Efficient GPUs

Architecting energy efficient crossbar-based memristive random-access memories

Compact Modeling and System Implications of Microring Modulators in Nanophotonic Interconnects

DWDM Nanophotonic Interconnects: Toward Terabit/s Chip-Scale Serial Link

Feature Engineering With Canonical Analysis for Effective Statistical Tests Screening Test Escapes

Hardware Trojan detection using exhaustive testing of k-bit subspaces

Hardware Trojans Hidden in RTL Don’t Cares – Automated Insertion and Prevention Methodologies

HReRAM: A Hybrid Reconfigurable Resistive Random-Access Memory

Leveraging Nonvolatility for Architecture Design with Emerging NVM

Standard 12-lead ECG Synthesis Using a GA Optimized BP Neural Network

Toward large-scale access-transistor-free memristive crossbars

Variation-Aware Adaptive Tuning for Nanophotonic Interconnects

Vertical Integration of Memristors onto Foundry CMOS Dies using Wafer-Scale Integration

Vision-inertial Hybrid Tracking for Robust and Efficient Augmented Reality on Smartphones

Compact Test Generation With an Influence Input Measure for Launch-On-Capture Transition Fault Testing

Learning Optimized Local Difference Binaries for Scalable Augmented Reality on Mobile Devices

Local Difference Binary for Ultrafast and Distinctive Feature Description

Test-Quality Optimization for Variable n-Detections of Transition Faults

Thermal stress implications in athermal TiO₂ waveguides on a silicon substrate

Athermal characteristics of TiO₂-clad silicon waveguides at 1.3μm

Energy-efficient GPGPU Architectures via Collaborative Compilation and Memristive Memory-based Computing

Geodesic Active Contours with Adaptive Configuration for Cerebral Vessel and Aneurysm Segmentation

Joint Virtual Probe: Joint Exploration of Multiple Test Items' Spatial Patterns for Efficient Silicon Characterization and Test Prediction

Learning from Production Test Data: Correlation Exploration and Feature Engineering

libLDB: A library for extracting ultrafast and distinctive binary feature description

Low-Cost Error Tolerance Scheme for 3-D CMOS Imagers

Architecting Low Power Crossbar-Based Memristive RAM

Digital-to-analog and Analog-to-digital Conversion with Metal Oxide Memristors for Ultra-low Power Computing

Mutation Analysis with Coverage Discounting

Performance Optimization of Vision Apps on Mobile Application Processor

Role of Thermal Stress in Athermal Waveguide Design Using TiO₂ Waveguides on a Silicon Substrate

Test Data Analytics - Exploring Spatial and Test-item Correlations in Production Test Data

Towards Data Reliable Crossbar-based Memristive Memories

Power-Efficient Calibration and Reconfiguration for Optical Network-on-Chip

3D CMOS-memristor hybrid circuits: devices, integration, architecture, and applications

Accelerating SURF detector on mobile devices

Adaptive test selection for post-silicon timing validation: A data mining approach

Comprehensive online defect diagnosis in on-chip networks

Energy and performance characterization of mobile heterogeneous computing

Energy-Aware Real-Time Face Recognition System on Mobile CPU-GPU Platform

Improving Validation Coverage Metrics to Account for Limited Observability

LDB: An ultra-fast feature for scalable augmented reality on mobile devices

On Error Modeling of Electrical Bugs for Post-Silicon Timing Validation

Platform characterization for domain-specific computing

Post-fabrication reconfiguration for power-optimized tuning of optically connected multi-core systems

Power-Efficient Calibration and Reconfiguration for On-Chip Optical Communication

A Promising Alternative to Conventional Silicon

Fast Visual Retrieval Using Accelerated Sequence Matching

Modeling Yield, Cost, and Quality of a Spare-Enhanced Multicore Chip

Organic Pseudo-CMOS Circuits for Low-Voltage Large-Gain High-Speed Operation

Pseudo-CMOS: A Design Style for Low-Cost and Robust Flexible Electronics

Robust Circuit Design for Flexible Electronics

Tester-Assisted Calibration and Screening for Digitally-Calibrated ADCs

Time-Multiplexed Online Checking

An all-digital built-in self-test technique for transfer function characterization of RF PLLs

Coverage discounting: A generalized approach for testbench qualification

End-to-End Error Correction and Online Diagnosis for On-Chip Networks

Energy-optimized mapping of application to smartphone platform—a case study of mobile face recognition

GPU-accelerated fault simulation and its new applications

Image Quality Aware Metrics for Performance Specification of ADC Array in 3D CMOS Imagers

Image-Quality-Driven Metrics for Testing and Calibrating ADC Array in CMOS Imagers: A First Step

Large-scale EMM identification based on geometry-constrained visual word correspondence voting

Minimum Correspondence Sets for improving large-scale Augmented Paper

Organic Pseudo-CMOS for 2V Operational High-Speed Circuits

Post-silicon Bug Detection for Variation Induced Electrical Bugs

Test cost reduction through performance prediction using virtual probe

Using mobile GPU for general-purpose computing–a case study of face recognition on smartphones

Calibration and Test Time Reduction Techniques for Digitally-Calibrated Designs: an ADC Case Study

Recent Advances in Analog, Mixed-Signal, and RF Testing

Efficient Test Methodologies for High-Speed Serial Links

A Two-Tone Test Method for Continuous-Time Adaptive Equalizers

An Accurate Jitter Estimation Technique

An Efficient Jitter Measurement Technique

BER Estimation for Linear Clock and Data Recovery Circuit

BER Estimation for Non-Linear Clock and Data Recovery Circuit

Gaps in Timing Margining Test

Introduction

A case study of time-multiplexed assertion checking for post-silicon debugging

A GPU-accelerated face annotation system for smartphones

A Portable Multi-pitch e-Drum Based on Printed Flexible Pressure Sensors

An Automatic Test Generation Framework for Digitally-assisted Adaptive Equalizers in High-speed Serial Links

An Error Tolerance Scheme for 3D CMOS Imagers

Calibration-assisted production testing for digitally-calibrated ADCs

Design, analysis, and test of low-power and reliable flexible electronics

Error-locality-aware linear coding to correct multi-bit upsets in SRAMs

Innovative practices session 2C: Design, fabrication and test of flexible electronics

Low-cost quality assurance techniques for high-performance mixed-signal/RF circuits and systems

Mobile image search with multimodal context-aware queries

Modeling yield, cost, and quality of an NoC with uniformly and non-uniformly distributed redundancy

Mutation-based diagnostic test generation for hardware design error diagnosis

nGFSIM : A GPU-based fault simulator for 1-to-n detection and its applications

Pseudo-CMOS: A novel design style for flexible electronics

SCEMIT: A SystemC error and mutation injection tool

SEChecker: A Sequential Equivalence Checking Framework Based on Kth Invariants

What is flexible electronics?

Electronic design automation: synthesis, verification, and test

A built-in self-calibration scheme for pipelined ADCs

An experimental study on content-based face annotation of photos

An Instrumented Observability Coverage Method for System Validation

Calibration and testing time reduction techniques for a digitally-calibrated pipelined ADC

Calibration as a functional test: An ADC case study

Design for low power and reliable flexible electronics: Self-tunable cell-library design

Dynamic Test Compaction for Transition Faults in Broadside Scan Testing Based on an Influence Cone Measure

Low Overhead Time-Multiplexed Online Checking: A Case Study of An H.264 Decoder

MyFinder: near-duplicate detection for large image collections

Near-duplicate detection for images and videos

TAC: Testing time reduction for digitally-calibrated designs

Test strategies for adaptive equalizers

Video copy detection by fast sequence matching

Yield and cost analysis of a reliable NoC

A 1.25-KS/s 3-bit Flash ADC in A-Si:H TFTs for Flexible Sensors

A Clock-Less Jitter Spectral Analysis Technique

Digitally-Assisted Production Testing of a Digitally Calibrated RF Receiver

G.P.11.07 Impairment of the endosomal/lysosomal system may contribute to muscle wasting in Pompe disease by altering the trafficking and processing of membrane stabilizing proteins

Logic Testing

Reliability Analysis for Flexible Electronics: Case Study of Integrated a-Si:H TFT Scan Driver

Time-Multiplexed Online Checking: Resilient Design for Cost-Sensitive SoCs

A cost analysis framework for multi-core systems with spares

A real-time, embedded face-annotation system

A string matching approach for visual retrieval and classification

Accurate Bit-Error-Rate estimation for efficient high speed I/O testing

Bit-error rate estimation for bang-bang clock and data recovery circuit in high-speed serial links

Digitally-assisted analog/RF testing for mixed-signal SoCs

RTL error diagnosis using a word-level SAT-solver

Time-Multiplexed Online Checking: A Feasibility Study

Multiple-fault diagnosis based on adaptive diagnostic test pattern generation

Silicon Debug for Timing Errors

Summary of Current Activities

A framework for system reliability analysis considering both system error tolerance and component test quality

A hybrid scheme for compacting test responses with unknown values

A two-tone test method for continuous-time adaptive equalizers

An accurate jitter estimation technique for efficient high speed I/O testing

An Efficient Diagnostic Test Pattern Generation Framework Using Boolean Satisfiability

Diagnosing scan chains using SAT-based diagnostic pattern generation

Reliability analysis for flexible electronics: Case study of integrated a-Si:H TFT scan driver

Testable Design for Advanced Serial-Link Transceivers

Annual index

Bit-Error-Rate Estimation for High-Speed Serial Links

Digitally-Assisted Analog Test, Characterization and Tuning for Mixed-Signal Systems

Failure Modeling Cluster

New beginnings, continued success

Pseudofunctional testing

System-Aware Test and Automatic Diagnosis for Sub-Systems

The New World of ESL Design

Vision from the Top

Automatic Test Pattern Generation

A Unified Approach to Test Generation and Test Data Volume Reduction

Bit Error Rate Estimation for Improving Jitter Testing of High-Speed Serial Links

Coverage Loss By Using Space Compactors in Presence of Unknown Values

Efficient identification of multi-cycle false path

Fast Human Detection Using a Cascade of Histograms of Oriented Gradients

Generation of shorter sequences for high resolution error diagnosis using sequential SAT

IChecker: An Efficient Checker for Inductive Invariants

Multimodal fusion using learned text concepts for image categorization

Multiple-Fault Diagnosis Based on Single-Fault Activation and Single-Output Observation

On usage models of content-based image search, filtering, and annotation

Simulation-Based Functional Test Generation for Embedded Processors

Testable Design for Adaptive Linear Equalizer in High-Speed Serial Links

Timing-reasoning-based delay fault diagnosis

Unknown-tolerance analysis and test-quality control for test response compaction using space compactors

Using 2-domain partitioned OBDD data structure in an enhanced symbolic simulator

Embedded Software-Based Self-Testing for SoC Design

Accurate diagnosis of multiple faults

An efficient sequential SAT solver with improved search strategies

ChiYun compact: a novel test compaction technique for responses with unknown values

Constraint extraction for pseudo-functional scan-based delay testing

Efficient conflict-based learning in an RTL circuit constraint solver

Learning a sparse, corner-based representation for time-varying background modelling

On a software-based self-test methodology and its application

On statistical correlation based path selection for timing validation

Production-oriented interface testing for PCI-Express by enhanced loop-back technique

Pseudo-functional scan-based BIST for delay fault

Response shaper: a novel technique to enhance unknown tolerance for output response compaction

RTL SAT simplification by boolean and interval arithmetic reasoning

Sequential equivalence checking based on K-th invariants and circuit SAT solving

Simulation-based functional test generation for embedded processors

Simulation-based target test generation techniques for improving the robustness of a software-based-self-test methodology

Structural search for RTL with predicate learning

Using visual features for anti-spam filtering

A new sigma-delta modulator architecture for testing using digital stimulus

A signal correlation guided circuit-SAT solver

Critical path selection for delay fault testing based upon a statistical timing model

New challenges in delay testing of nanometer, multigigahertz designs

Safety property verification using sequential SAT and bounded model checking

Self-referential verification for gate-level implementations of arithmetic circuits

A path-based methodology for post-silicon timing validation

A scalable on-chip jitter extraction technique

A unified adaptive approach to accurate skin detection

A Σ-Δ modulation based analog BIST system with a wide bandwidth fifth-order analog response extractor for diagnosis purpose

Adaptive learning of an accurate skin-color model

An adaptive skin model and its application to objectionable image filtering

An efficient finite-domain constraint solver for circuits

BER estimation for serial links based on jitter spectrum and clock recovery characteristics

Efficient reachability checking using sequential SAT

Improved symbolic simulation by functional-space decomposition

Improved symoblic simulation by dynamic funtional space partitioning

Jitter spectral extraction for multi-gigahertz signal

On path-based learning and its applications in delay test and diagnosis

On using a 2-domain partitioned OBDD data structure in verification

Pattern selection for testing of deep sub-micron timing defects

Random jitter extraction technique in a multi-gigahertz signal

SSD tracking using dynamic template and Log-polar transformation

Static statistical timing analysis for latch-based pipeline designs

TranGen: A SAT-based ATPG for path-oriented transition faults

A Multimodal Image Database System

An anatomy of a large-scale image search engine

Critical Path Selection for Deep Sub-Micron Delay Test and Timing Validation

DfT Sigma-Delta Modulator Architecture Implementation

Enhanced Symbolic Simulation for Functional Verification of Embedded Array Systems

Guest editors' introduction: Speed test and speed binning for complex ICs

Modeling, testing, and analysis for delay defects and noise effects in deep submicron devices

Practical considerations in applying Σ-Δ modulation-based analog BIST to sampled-data systems

SHIVA – A Fast Hybrid Constraint Solver for Circuits

Special Section on VLSI Design and CAD Algorithms-Timing Verification and Test Generation-Critical Path Selection for Deep Sub-Micron Delay Test and Timing Validation

A circuit SAT solver with signal correlation guided learning

A comparison of BDDs, BMC, and sequential SAT for model checking

A signal correlation guided ATPG solver and its applications for solving difficult industrial cases

Delay defect diagnosis based upon a statistical timing model - The first step

Delay defect diagnosis based upon statistical timing models - The first step

Delta-sigma modulator based mixed-signal BIST architecture for SoC

Diagnosis of delay defects using statistical timing models

Diagnosis-Based Post-Silicon Timing Validation Using Statistical Tools and Methodologies

Enhancing diagnosis resolution for delay defects based upon statistical timing and statistical fault models

Experience in critical path selection for deep sub-micron delay test and timing validation

Multimedia web services for content filtering, searching, and digital rights management

On structural vs. functional testing for delay faults

SATORI - A fast sequential sat engine for circuits

Test consideration for nanometer scale CMOS circuits

The Confluence of Manufacturing Test and Design Validation

Using Logic Models to Predict the Detection Behavior of Statistical Timing Defects

Embedded software-based self-test for programmable core-based designs

An Enhanced BIST Scheme for ADC and Non-monotonic DAC

Analysis of delay test effectiveness with a multiple-clock scheme

Combining ATPG and symbolic simulation for efficient validation of embedded array systems

Embedded Software-Based Self-Testing for SoC Design

Enhancing test efficiency for delay fault testing using multiple-clocked schemes

False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation

Hybrid learning schemes for multimedia information retrieval

MORF: A distributed multimodal information filtering system

On the development of ATPG based Satisfiability Checker

On theoretical and practical considerations of path selection for delay fault testing

On-chip analog response extraction with 1-bit Σ-Δ modulators

PBIR-MM: Multimodal image retrieval and annotation

Self-referential verification of gate-level implementations of arithmetic circuits

Self-testing second-order delta-sigma modulators using digital stimulus

Software-based weighted random testing for IP cores in bus-based programmable SoCs

Supporting subjective image queries without seeding requirements - Proposing test queries for Benchathlon

Testing second-order delta-sigma modulators using pseudo-random patterns

Limitations and challenges of computer-aided design technology for CMOS VLSI

Pattern generation for delay testing and dynamic timing analysis considering power-supply noise effects

Using word-level ATPG and modular arithmetic constraint-solving techniques for assertion property checking

Vector generation for power supply noise estimation and verification of deep submicron designs

Verifying sequential equivalence using ATPG techniques

A self-test methodology for IP cores in bus-based programmable SoCs

An analysis of ATPG and SAT algorithms for formal verification

An on-chip short-time interval measurement technique for testing high-speed communication links

Delay testing considering crosstalk-induced effects

Embedded-software-based approach to testing crosstalk-induced faults at on-chip buses

Fast statistical timing analysis by probabilistic event propagation

HRM - A hierarchical simulator for full-chip power network reliability analysis

Induction-based gate-level verification of multipliers

Instruction-level DfT for testing processor and IP cores in system-on-a-chip

Mining image features for efficient query processing

PBIR - Perception-based image retrieval

PBIR: Perception-Based Image Retrieval-A system that can quickly capture subjective image query concepts

Support vector machine pairwise classifiers with error reduction for image classification

SVM binary classifier ensembles for image classification

AQUILA: An equivalence checking system for large sequential designs

Estimation for maximum instantaneous current through supply lines for CMOS circuits

Functionally testable path delay faults on a microprocessor

On improving test quality of scan-based BIST

Test point selection for analog fault diagnosis of unpowered circuit boards

Testable path delay fault cover for sequential circuits

A BIST scheme for on-chip ADC and DAC testing

A delta-sigma modulation based BIST scheme for mixed-signal systems

A sigma-delta modulation based BIST scheme for mixed-signal circuits

A testability metric for path delay faults and its application

An FPGA-based re-configurable functional tester for memory chips

Assertion checking by combined word-level ATPG and modular arithmetic constraint-solving techniques

Characterization of a pseudo-random testing technique for analog and mixed-signal built-in-self-test

Collaboration between industry and academia in test research

Dynamic timing analysis considering power supply noise effects

Efficient test mode selection and insertion for RTL-BIST

On testing the path delay faults of a microprocessor using its instruction set

Path selection and pattern generation for dynamic timing analysis considering power supply noise effects

Path selection for delay testing of deep sub-micron devices using statistical performance sensitivity analysis

Performance sensitivity analysis using statistical methods and its applications to delay testing

Static property checking using ATPG v.s. BDD techniques

Test challenges for deep sub-micron technologies

Test program synthesis for path delay faults in microprocessor cores

Testing and characterization of the one-bit first-order delta-sigma modulator for on-chip analog signal analysis

AutoFix: A hybrid tool for automatic logic rectification

Current Directions in Automatic Test-Pattern Generation

ErrorTracer: Design error diagnosis based on fault simulation techniques

Fault emulation: A new methodology for fault grading

Primitive delay faults: Identification, testing, and design for testability

Test generation for linear time-invariant analog circuits

A new bare die test methodology

Analysis of performance impact caused by power supply noise in deep submicron devices

Delay testing considering power supply noise effects

Improving the test quality for scan-based BIST using a general test application scheme

Specification back-propagation and its application to DC fault simulation for analog/mixed-signal circuits

Testing high speed VLSI devices using slower testers

VIP - an input pattern generator for identifying critical voltage drop for deep sub-micron designs

A hybrid methodology for switching activities estimation

Efficient test-point selection for scan-based BIST

Test-point insertion: scan paths through functional logic

Delay Fault Testing for VLSI Circuits

Algorithm for Verifying Retimed Circuits

AQUILA: A Local BDD-based Equivalence Verifier

Case Studies on Delay Testing

Conclusions and Future Work

Delay Fault Models

Delay Fault Simulation

Design for Delay Fault Testability

ErrorTracer: Error Diagnosis by Fault Simulation

Extension to Sequential Error Diagnosis

Incremental logic rectification

Incremental Verification for Combinational Circuits

Incremental Verification for Sequential Circuits

Introduction to Logic Debugging

Path Delay Fault Classification

RTL-to-Gate Verification

Symbolic Verification

Synthesis for Delay Fault Testability

Test Application Schemes for Testing Delay Defects

Test Generation for Path Delay Faults

A hybrid power model for RTL power estimation

An almost full-scan BIST solution - higher fault coverage and shorter test application time

Estimation of maximum power supply noise for deep sub-micron designs

Exact and approximate estimation for maximum instantaneous current of CMOS circuits

Fault-simulation based design error diagnosis for sequential circuits

Functional scan chain testing

LIBRA - a library-independent framework for post-layout performance optimization

National Science Foundation Workshop on future research directions in testing of electronic circuits and systems

Postlayout logic restructuring using alternative wires

Pseudorandom testing for mixed-signal circuits

Resynthesis of Combinational Circuits for Path Count Reduction and for Path Delay Fault Testability

A Hybrid algorithm for test point selection for scan-based BIST

Analog fault diagnosis for unpowered circuit boards

AQUILA: An equivalence verifier for large sequential circuits

Design for primitive delay fault testability

ErrorTracer: A fault simulation-based approach to design error diagnosis

Estimation of maximum power and instantaneous current using a genetic algorithm

Fault macromodeling for analog/mixed-signal circuits

Incremental logic rectification

Post-layout logic restructuring for performance optimization

Test synthesis approach to reducing BALLAST DFT overhead

Vector generation for maximum instantaneous current through supply lines for CMOS circuits

Automatic generation of functionial vectors using the extended finite state machine model

Classification and identification of nonrobust untestable path delay faults

Design Validation: Formal Verification vs. Simulation vs. Functional Testing

Fault macromodeling and a testing strategy for opamps

Generation of high quality tests for robustly untestable path delay faults

Perturb and simplify: multilevel boolean network optimizer

Tutorial and Survey Paper: Gate-Level test generation for sequential circuits

An ATPG-based framework for verifying sequential equivalence

An Efficient compact test generator for IDDQ testing

Built-In Self Test for Analog and Mixed-Signal Designs

Compact vector generation for accurate power simulation

Driving toward higher IDDQ test quality for sequential circuits: A generalized fault model and its ATPG

Error correction based on verification techniques

Identification and test generation for primitive faults

Implicit functional testing for analog circuits

New hybrid methodology for power estimation

Novel methodology for transistor-level power estimation

On verifying the correctness of retimed circuits

Scan paths through functional logic

Test point insertion: Scan paths through combinational logic

Testable path delay fault cover for sequential circuits

Single-Clock Partial Scan

Test synthesis: the practicality of DFT

Timing-Driven Partial Scan

An Efficient algorithm for local don't care sets calculation

Fast identification of robust dependent path delay faults

Fault emulation: A new approach to fault grading

Generation of high quality tests for functional sensitizable paths

Logic optimization by an improved sequential redundancy addition and removal technique

Logic synthesis for engineering change

Minimax end-to-end delay routing and capacity assignment for virtual circuit networks

Partial scan designs without using a separate scan clock

Pseudo-random testing and signature analysis for mixed-signal circuits

Speeding up power estimation by topological analysis

Timing-driven test point insertion for full-scan and partial-scan BIST

Automatic test generation for digital electronic circuits

Comprehensive fault macromodel for opamps

Generation of high quality non-robust tests for path delay faults

Layout driven logic synthesis for FPGAs

On the computation of the set of reachable states of hybrid models

On the joint virtual path assignment and virtual circuit routing problem in ATM networks

Test Synthesis in Cooperation with the International Test Conference

Delay-Fault Test Generation and Synthesis for Testability Under a Standard Scan Design Methodology

On the over-specification problem in sequential ATPG algorithms

Redundancy Removal for Sequential Circuits Without Reset States

STOIC: State Assignment Based on Output/Input Functions

Transition Fault Testing for Sequential Circuits

Automatic functional test generation using the extended finite state machine model

Delay testing for non-robust untestable circuits

Multi-chip Modules Introduction

Multi-level logic optimization by redundancy addition and removal

Sequential logic optimization by redundancy addition and removal

Virtual path assignment and virtual circuit routing in ATM networks

A Functional Fault Model for Sequential Machines

Initializability Consideration in Sequential Machine Synthesis

A partial enhanced-scan approach to robust delay-fault test generation for sequential circuits

An ATPG-based approach to sequential logic optimization

On the over-specification problem in sequential ATPG algorithms

State assignment using input/output functions

Test generation for delay faults in non-scan and partial scan sequential circuits

Timing-driven partial scan

Transition fault simulation for sequential circuits

Methods for synthesizing testable sequential circuits

Behavioral and logic synthesis for performance and testability

On removing redundancy in sequential circuits

Pascant: A partial scan and test generation system

Robust delay-fault test generation and synthesis for testability under a standard scan design methodology

Test function specification in synthesis

A Partial Scan Method for Sequential Circuits with Feedback

A Simulation-Based Method for Generating Tests for Sequential Circuits

Finite state machine synthesis with embedded test function

A single-state-transition fault model for sequential machines

An architecture for synthesis of testable finite state machines

An entropy measure for the complexity of multi-output Boolean functions

Functional test generation for finite state machines

Synthesis of testable finite state machines

Timing optimization with testability considerations

A Directed Search Method for Test Generation Using a Concurrent Simulator

Unified Methods for VLSI Simulation and Test Generation

Concurrent test generation and design for testability

Design of sequential machines for efficient test generation

Economical scan design for sequential logic test generation

Fault simulation in a pipelined multiprocessor system

State assignment for initializable synthesis

Designing circuits with partial scan

Threshold-value Simulation and Test Generation

CONTEST: A concurrent test generator for sequential circuits.

Sequential circuit test generation using threshold-value simulation

Complete solution to the partial scan problem

Simulation-based directed-search method for test generation

An Approach to structural optimization—sequential quadratic programming, SQP

Sequential Quadratic Programming and Dynamic Optimal Design of Rotating Blades

A Three-stage Deep Learning Model for Accurate Retinal Vessel Segmentation

Article

A Two-Stage Convolutional Neural Network for Pulmonary Embolism Detection From CTPA Images

Article

Bayesian DeNet: Monocular Depth Prediction and Frame-wise Fusion with Synchronized Uncertainty

Article

Compact Modeling of Thin-Film Transistors for Flexible Hybrid IoT Design

Article

Low-voltage High-performance Flexible Digital and Analog Circuits Based on Ultrahigh-purity Semiconducting Carbon Nanotubes

Article

Process Design Kit and Design Automation for Flexible Hybrid Electronics

Article

Reactive obstacle avoidance of monocular quadrotors with online adapted depth prediction network

Article

Real-Time Dense Monocular SLAM With Online Adapted Depth Prediction Network

Article

Real-time Semantic Plane Reconstruction on a Monocular Drone Using Sparse Fusion

Article

Automated Pulmonary Embolism Detection from CTPA Images Using an End-to-End Convolutional Neural Network

Conference paper

Bidirectional tuning of microring-based silicon photonic transceivers for optimal energy efficiency

Conference paper

Evaluating Assertion Set Completeness to Expose Hardware Trojans and Verification Blindspots

Conference paper

Latent weights do not exist: Rethinking binarized neural network optimization

Conference paper

Learning to Capture a Film-Look Video with a Camera Drone

Conference paper

Learning to Film from Professional Human Motion Videos

Conference paper

MetaPruning: Meta Learning for Automatic Neural Network Channel Pruning

Conference paper

Pre-silicon Formal Verification of JTAG Instruction Opcodes for Security

Conference paper

Process design kit and design automation for flexible hybrid electronics

Conference paper

Process Design Kit and Design Automation for Flexible Hybrid Electronics

Conference paper

Process Design Kit and Design Automation for Flexible Hybrid Electronics

Conference paper

Taming Emerging Devices' Variation and Reliability Challenges with Architectural and System Solutions [Invited]

Conference paper

Task mapping-assisted laser power scaling for optical network-on-chips

Conference paper

Ultra-thin Skin Electronics for High Quality and Continuous Skin-Sensor-Silicon Interfacing

Conference paper

Visualizing the Decision-making Process in Deep Neural Decision Forest

Conference paper

A Lightweight Piecewise Linear Synthesis Method for Standard 12-lead ECG Signals Based on Adaptive Region Segmentation

Article

A Skeletal Similarity Metric for Quality Evaluation of Retinal Vessel Segmentation

Article

Accurate Face Alignment and Adaptive Patch Selection for Heart Rate Estimation From Videos Under Realistic Scenarios

Article

Automated Detection of Clinically Significant Prostate Cancer in mp-MRI Images Based on an End-to-End Deep Neural Network

Article

Joint Segment-Level and Pixel-Wise Losses for Deep Learning Based Retinal Vessel Segmentation

Article

Resistive random-access memory based on ratioed memristors

Article

Robust and Real-time Pose Tracking for Augmented Reality on Mobile Devices

Article

A Deep Model with Shape-preserving Loss for Gland Instance Segmentation

Conference paper

ACT: An Autonomous Drone Cinematography System for Action Scenes

Conference paper

Bi-Real Net: Enhancing the Performance of 1-bit CNNs with Improved Representational Capability and Advanced Training Algorithm

Conference paper

Compact Modeling of Carbon Nanotube Thin Film Transistors for Flexible Circuit Design

Conference paper

Energy-Efficient Channel Alignment of DWDM Silicon Photonic Transceivers

Conference paper

Fully Printed Organic Pseudo-CMOS Circuits for Sensing Applications

Conference paper

Monocular Camera Based Real-time Dense Mapping Using Generative Adversarial Network

Conference paper

Pairing of Microring-based Silicon Photonic Transceivers for Tuning Power Optimization

Conference paper

Process Design Kit for Flexible Hybrid Electronics

Conference paper

StitchAD-GAN for Synthesizing Apparent Diffusion Coefficient Images of Clinically Significant Prostate Cancer

Conference paper

Through-the-Lens Drone Filming

Conference paper

A multiply-add engine with monolithically integrated 3D memristor crossbar/CMOS hybrid circuit

Article

An Automated Method for Accurate Vessel Segmentation

Article

Automated Diagnosis of Prostate Cancer in Multi-Parametric MRI Based on Multimodal Convolutional Neural Networks

Article

Compact Modeling for Silicon Photonic Heterogeneously Integrated Circuits

Article

Co-trained Convolutional Neural Networks for Automated Detection of Prostate Cancer in Multi-parametric MRI

Article

Hiding Hardware Trojan Communication Channels in Partially Specified SoC Bus Functionality

Article

Verification and Trust for Unspecified IP Functionality

Book chapter

3D-DPE: A 3D High-Bandwidth Dot-Product Engine for High-Performance Neuromorphic Computing

Conference paper

An Artificial Neural Network Approach for Screening Test Escapes

Conference paper

Compact Modeling and Circuit-Level Simulation of Silicon Nanophotonic Interconnects

Conference paper

Detecting Hardware Trojans in Unspecified Functionality through Solving Satisfiability Problems

Conference paper

DLPS: Dynamic Laser Power Scaling for Optical Network-on-Chip

Conference paper

Joint Detection and Diagnosis of Prostate Cancer in Multi-parametric MRI Based on Multimodal Convolutional Neural Networks

Conference paper

Mining Mutation Testing Simulation Traces for Security and Testbench Debugging

Conference paper

REDBEE: A visual-inertial drone system for real-time moving object detection

Conference paper

Robust Design and Design Automation for Flexible Hybrid Electronics

Conference paper

An Efficient Network-on-Chip Yield Estimation Approach Based on Gibbs Sampling

Article

Associative Memristive Memory for Approximate Computing in GPUs

Article

Renal Compartment Segmentation in DCE-MRI Images

Article

Automatic Test Pattern Generation

Book chapter

A Low-Power Hybrid Reconfigurable Architecture For Resistive Random-Access Memories

Conference paper

A Wearable Signal Acquisition System for Physiological Signs Including Throat PPG

Conference paper

Accurate and Efficient Pulse Measurement from Facial Videos on Smartphones

Conference paper

Detecting Hardware Trojans in Unspecified Functionality Using Mutation Testing

Conference paper

Hardware Trojans in Incompletely Specified On-chip Bus Systems

Conference paper

In-place Repair for Resistive Memories Utilizing Complementary Resistive Switches

Conference paper

Large-Signal Model for Small-Size High-Speed Carrier-Injection Silicon Microring Modulator

Conference paper

Local Feature Descriptor Learning with Adaptive Siamese Network

Conference paper

OGB: A Distinctive and Efficient Feature for Mobile Augmented Reality

Conference paper

Pairwise Proximity-Based Features for Test Escape Screening

Conference paper

Printed Circuits on Flexible Substrates: Opportunities and Challenges (invited paper)

Conference paper

Process-variation tolerant flexible circuit for wearable electronics

Conference paper

Spatial Pattern Analysis of Process Variations in Silicon Microring Modulators

Conference paper

Trojans Modifying Soft-Processor Instruction Sequences Embedded in FPGA Bitstreams

Conference paper

Variation and Failure Characterization Through Pattern Classification of Test Data From Multiple Test Stages

Conference paper

A low-Power Variation-Aware Adaptive Write Scheme for Access-Transistor-Free Memristive Memory

Article

A Power Efficient Test Data Compression Method on Count Compatible PRL Coding

Article

Athermal silicon ring resonators clad with titanium dioxide for 1.3µm wavelength operation

Article

Compact models for carrier-injection silicon microring modulators

Article

Design, Automation, and Test for Low-Power and Reliable Flexible Electronics

Article

Mobile Image Search: Challenges and Methods

Book chapter

[POSTER] Fusion of Vision and Inertial Sensing for Accurate and Efficient Pose Tracking on Smartphones

Conference paper

20 Gb/s Carrier-Injection Silicon Microring Modulator with SPICE-Compatible Dynamic Model

Conference paper

A Configurable CMOS Memory Platform for 3D-Integrated Memristors

Conference paper

Accurate Vessel Segmentation with Progressive Contrast Enhancement and Canny Refinement

Conference paper

AdaTest: An Efficient Statistical Test Framework for Test Escape Screening

Conference paper

Approximate Associative Memristive Memory for Energy-Efficient GPUs

Conference paper

Architecting energy efficient crossbar-based memristive random-access memories

Conference paper

Compact Modeling and System Implications of Microring Modulators in Nanophotonic Interconnects

Conference paper

DWDM Nanophotonic Interconnects: Toward Terabit/s Chip-Scale Serial Link

Conference paper

Feature Engineering With Canonical Analysis for Effective Statistical Tests Screening Test Escapes

Conference paper

Hardware Trojan detection using exhaustive testing of k-bit subspaces

Conference paper

Hardware Trojans Hidden in RTL Don’t Cares – Automated Insertion and Prevention Methodologies

Conference paper

HReRAM: A Hybrid Reconfigurable Resistive Random-Access Memory

Conference paper

Leveraging Nonvolatility for Architecture Design with Emerging NVM

Conference paper

Standard 12-lead ECG Synthesis Using a GA Optimized BP Neural Network

Conference paper

Toward large-scale access-transistor-free memristive crossbars

Conference paper

Variation-Aware Adaptive Tuning for Nanophotonic Interconnects

Conference paper

Vertical Integration of Memristors onto Foundry CMOS Dies using Wafer-Scale Integration

Conference paper

Vision-inertial Hybrid Tracking for Robust and Efficient Augmented Reality on Smartphones

Conference paper

Compact Test Generation With an Influence Input Measure for Launch-On-Capture Transition Fault Testing

Article

Learning Optimized Local Difference Binaries for Scalable Augmented Reality on Mobile Devices

Article

Local Difference Binary for Ultrafast and Distinctive Feature Description

Article

Test-Quality Optimization for Variable n-Detections of Transition Faults

Article

Thermal stress implications in athermal TiO₂ waveguides on a silicon substrate

Article

Athermal characteristics of TiO₂-clad silicon waveguides at 1.3μm

Conference paper

Energy-efficient GPGPU Architectures via Collaborative Compilation and Memristive Memory-based Computing

Conference paper

Geodesic Active Contours with Adaptive Configuration for Cerebral Vessel and Aneurysm Segmentation

Conference paper

Joint Virtual Probe: Joint Exploration of Multiple Test Items' Spatial Patterns for Efficient Silicon Characterization and Test Prediction

Conference paper

Learning from Production Test Data: Correlation Exploration and Feature Engineering

Conference paper

libLDB: A library for extracting ultrafast and distinctive binary feature description

Conference paper

Low-Cost Error Tolerance Scheme for 3-D CMOS Imagers

Article

Architecting Low Power Crossbar-Based Memristive RAM

Conference paper

Digital-to-analog and Analog-to-digital Conversion with Metal Oxide Memristors for Ultra-low Power Computing

Conference paper

Mutation Analysis with Coverage Discounting

Conference paper

Performance Optimization of Vision Apps on Mobile Application Processor

Conference paper

Role of Thermal Stress in Athermal Waveguide Design Using TiO₂ Waveguides on a Silicon Substrate

Conference paper

Test Data Analytics - Exploring Spatial and Test-item Correlations in Production Test Data

Conference paper

Towards Data Reliable Crossbar-based Memristive Memories

Conference paper

Power-Efficient Calibration and Reconfiguration for Optical Network-on-Chip

Article

3D CMOS-memristor hybrid circuits: devices, integration, architecture, and applications

Conference paper

Accelerating SURF detector on mobile devices

Conference paper

Adaptive test selection for post-silicon timing validation: A data mining approach

Conference paper

Comprehensive online defect diagnosis in on-chip networks

Conference paper

Energy and performance characterization of mobile heterogeneous computing

Conference paper

Energy-Aware Real-Time Face Recognition System on Mobile CPU-GPU Platform

Conference paper

Improving Validation Coverage Metrics to Account for Limited Observability

Conference paper

LDB: An ultra-fast feature for scalable augmented reality on mobile devices

Conference paper

On Error Modeling of Electrical Bugs for Post-Silicon Timing Validation

Conference paper

Platform characterization for domain-specific computing

Conference paper

Post-fabrication reconfiguration for power-optimized tuning of optically connected multi-core systems

Conference paper

Power-Efficient Calibration and Reconfiguration for On-Chip Optical Communication

Conference paper

A Promising Alternative to Conventional Silicon

Article

Fast Visual Retrieval Using Accelerated Sequence Matching

Article

Modeling Yield, Cost, and Quality of a Spare-Enhanced Multicore Chip

Article

Organic Pseudo-CMOS Circuits for Low-Voltage Large-Gain High-Speed Operation

Article

Pseudo-CMOS: A Design Style for Low-Cost and Robust Flexible Electronics

Article

Robust Circuit Design for Flexible Electronics

Article

Tester-Assisted Calibration and Screening for Digitally-Calibrated ADCs

Article

Time-Multiplexed Online Checking

Article

An all-digital built-in self-test technique for transfer function characterization of RF PLLs

Conference paper

Coverage discounting: A generalized approach for testbench qualification

Conference paper

End-to-End Error Correction and Online Diagnosis for On-Chip Networks

Conference paper

Energy-optimized mapping of application to smartphone platform—a case study of mobile face recognition

Conference paper

GPU-accelerated fault simulation and its new applications

Conference paper

Image Quality Aware Metrics for Performance Specification of ADC Array in 3D CMOS Imagers

Conference paper

Image-Quality-Driven Metrics for Testing and Calibrating ADC Array in CMOS Imagers: A First Step

Conference paper

Large-scale EMM identification based on geometry-constrained visual word correspondence voting

Conference paper

Minimum Correspondence Sets for improving large-scale Augmented Paper

Conference paper

Organic Pseudo-CMOS for 2V Operational High-Speed Circuits

Conference paper

Post-silicon Bug Detection for Variation Induced Electrical Bugs

Conference paper

Test cost reduction through performance prediction using virtual probe

Conference paper

Using mobile GPU for general-purpose computing–a case study of face recognition on smartphones

Conference paper

Calibration and Test Time Reduction Techniques for Digitally-Calibrated Designs: an ADC Case Study

Article

Recent Advances in Analog, Mixed-Signal, and RF Testing

Article

Efficient Test Methodologies for High-Speed Serial Links

Book

A Two-Tone Test Method for Continuous-Time Adaptive Equalizers

Book chapter

An Accurate Jitter Estimation Technique

Book chapter

An Efficient Jitter Measurement Technique

Book chapter

BER Estimation for Linear Clock and Data Recovery Circuit

Book chapter

BER Estimation for Non-Linear Clock and Data Recovery Circuit

Book chapter

Gaps in Timing Margining Test

Book chapter

Introduction

Book chapter

A case study of time-multiplexed assertion checking for post-silicon debugging

Conference paper

A GPU-accelerated face annotation system for smartphones

Conference paper

A Portable Multi-pitch e-Drum Based on Printed Flexible Pressure Sensors

Conference paper

An Automatic Test Generation Framework for Digitally-assisted Adaptive Equalizers in High-speed Serial Links

Conference paper

An Error Tolerance Scheme for 3D CMOS Imagers

Conference paper

Calibration-assisted production testing for digitally-calibrated ADCs

Conference paper

Design, analysis, and test of low-power and reliable flexible electronics

Conference paper

Error-locality-aware linear coding to correct multi-bit upsets in SRAMs

Conference paper

Innovative practices session 2C: Design, fabrication and test of flexible electronics

Conference paper

Low-cost quality assurance techniques for high-performance mixed-signal/RF circuits and systems

Conference paper

Mobile image search with multimodal context-aware queries

Conference paper

Modeling yield, cost, and quality of an NoC with uniformly and non-uniformly distributed redundancy

Conference paper

Mutation-based diagnostic test generation for hardware design error diagnosis

Conference paper

nGFSIM : A GPU-based fault simulator for 1-to-n detection and its applications

Conference paper

Pseudo-CMOS: A novel design style for flexible electronics

Conference paper

SCEMIT: A SystemC error and mutation injection tool

Conference paper

SEChecker: A Sequential Equivalence Checking Framework Based on Kth Invariants

Article

What is flexible electronics?

Article

Electronic design automation: synthesis, verification, and test

Book

A built-in self-calibration scheme for pipelined ADCs

Conference paper

An experimental study on content-based face annotation of photos

Conference paper

An Instrumented Observability Coverage Method for System Validation

Conference paper

Calibration and testing time reduction techniques for a digitally-calibrated pipelined ADC

Conference paper

Calibration as a functional test: An ADC case study

Conference paper

Design for low power and reliable flexible electronics: Self-tunable cell-library design

Conference paper

Dynamic Test Compaction for Transition Faults in Broadside Scan Testing Based on an Influence Cone Measure

Conference paper

Low Overhead Time-Multiplexed Online Checking: A Case Study of An H.264 Decoder

Conference paper

MyFinder: near-duplicate detection for large image collections

Conference paper

Near-duplicate detection for images and videos

Conference paper

TAC: Testing time reduction for digitally-calibrated designs

Conference paper

Test strategies for adaptive equalizers

Conference paper

Video copy detection by fast sequence matching

Conference paper

Yield and cost analysis of a reliable NoC

Conference paper

A 1.25-KS/s 3-bit Flash ADC in A-Si:H TFTs for Flexible Sensors

Article

A Clock-Less Jitter Spectral Analysis Technique

Article

Digitally-Assisted Production Testing of a Digitally Calibrated RF Receiver

Article

G.P.11.07 Impairment of the endosomal/lysosomal system may contribute to muscle wasting in Pompe disease by altering the trafficking and processing of membrane stabilizing proteins

Article

Logic Testing

Article

Reliability Analysis for Flexible Electronics: Case Study of Integrated a-Si:H TFT Scan Driver

Article

Time-Multiplexed Online Checking: Resilient Design for Cost-Sensitive SoCs

Article

A cost analysis framework for multi-core systems with spares

Conference paper

A real-time, embedded face-annotation system

Conference paper

A string matching approach for visual retrieval and classification

Conference paper

Accurate Bit-Error-Rate estimation for efficient high speed I/O testing

Conference paper

Bit-error rate estimation for bang-bang clock and data recovery circuit in high-speed serial links

Conference paper

Digitally-assisted analog/RF testing for mixed-signal SoCs

Conference paper

RTL error diagnosis using a word-level SAT-solver

Conference paper

Time-Multiplexed Online Checking: A Feasibility Study

Conference paper

Multiple-fault diagnosis based on adaptive diagnostic test pattern generation

Article

Silicon Debug for Timing Errors

Article

Summary of Current Activities

Article

A framework for system reliability analysis considering both system error tolerance and component test quality

Conference paper

A hybrid scheme for compacting test responses with unknown values

Conference paper

A two-tone test method for continuous-time adaptive equalizers

Conference paper

An accurate jitter estimation technique for efficient high speed I/O testing

Conference paper

An Efficient Diagnostic Test Pattern Generation Framework Using Boolean Satisfiability

Conference paper

Diagnosing scan chains using SAT-based diagnostic pattern generation

Conference paper

Reliability analysis for flexible electronics: Case study of integrated a-Si:H TFT scan driver

Conference paper

Testable Design for Advanced Serial-Link Transceivers

Conference paper

Annual index

Article

Bit-Error-Rate Estimation for High-Speed Serial Links

Article

Digitally-Assisted Analog Test, Characterization and Tuning for Mixed-Signal Systems

Article

Failure Modeling Cluster

Article

New beginnings, continued success

Article

Pseudofunctional testing

Article

System-Aware Test and Automatic Diagnosis for Sub-Systems

Article

The New World of ESL Design

Article

Vision from the Top

Article

Automatic Test Pattern Generation

Book chapter

A Unified Approach to Test Generation and Test Data Volume Reduction

Conference paper

Bit Error Rate Estimation for Improving Jitter Testing of High-Speed Serial Links

Conference paper

Coverage Loss By Using Space Compactors in Presence of Unknown Values

Conference paper

Efficient identification of multi-cycle false path

Conference paper

Fast Human Detection Using a Cascade of Histograms of Oriented Gradients

Conference paper

Generation of shorter sequences for high resolution error diagnosis using sequential SAT

Conference paper

IChecker: An Efficient Checker for Inductive Invariants

Conference paper

Multimodal fusion using learned text concepts for image categorization

Conference paper

Multiple-Fault Diagnosis Based on Single-Fault Activation and Single-Output Observation

Conference paper

On usage models of content-based image search, filtering, and annotation

Conference paper

Simulation-Based Functional Test Generation for Embedded Processors

Conference paper

Testable Design for Adaptive Linear Equalizer in High-Speed Serial Links

Conference paper

Timing-reasoning-based delay fault diagnosis

Conference paper

Unknown-tolerance analysis and test-quality control for test response compaction using space compactors

Conference paper

Using 2-domain partitioned OBDD data structure in an enhanced symbolic simulator

Article

Embedded Software-Based Self-Testing for SoC Design

Book chapter

Accurate diagnosis of multiple faults

Conference paper

An efficient sequential SAT solver with improved search strategies

Conference paper

ChiYun compact: a novel test compaction technique for responses with unknown values

Conference paper

Constraint extraction for pseudo-functional scan-based delay testing

Conference paper

Efficient conflict-based learning in an RTL circuit constraint solver

Conference paper

Learning a sparse, corner-based representation for time-varying background modelling

Conference paper

On a software-based self-test methodology and its application

Conference paper

On statistical correlation based path selection for timing validation

Conference paper

Production-oriented interface testing for PCI-Express by enhanced loop-back technique

Conference paper

Pseudo-functional scan-based BIST for delay fault

Conference paper

Response shaper: a novel technique to enhance unknown tolerance for output response compaction

Conference paper

RTL SAT simplification by boolean and interval arithmetic reasoning

Conference paper

Sequential equivalence checking based on K-th invariants and circuit SAT solving

Conference paper

Simulation-based functional test generation for embedded processors

Conference paper

Simulation-based target test generation techniques for improving the robustness of a software-based-self-test methodology

Conference paper

Structural search for RTL with predicate learning

Conference paper

Using visual features for anti-spam filtering

Conference paper

A new sigma-delta modulator architecture for testing using digital stimulus

Article

A signal correlation guided circuit-SAT solver

Article

Critical path selection for delay fault testing based upon a statistical timing model

Article

New challenges in delay testing of nanometer, multigigahertz designs

Article

Safety property verification using sequential SAT and bounded model checking

Article

Self-referential verification for gate-level implementations of arithmetic circuits

Article

A path-based methodology for post-silicon timing validation

Conference paper

A scalable on-chip jitter extraction technique

Conference paper

A unified adaptive approach to accurate skin detection

Conference paper

A Σ-Δ modulation based analog BIST system with a wide bandwidth fifth-order analog response extractor for diagnosis purpose

Conference paper

Adaptive learning of an accurate skin-color model

Conference paper

An adaptive skin model and its application to objectionable image filtering

Conference paper

An efficient finite-domain constraint solver for circuits

Conference paper

BER estimation for serial links based on jitter spectrum and clock recovery characteristics

Conference paper

Efficient reachability checking using sequential SAT

Conference paper

Improved symbolic simulation by functional-space decomposition

Conference paper

Improved symoblic simulation by dynamic funtional space partitioning

Conference paper

Jitter spectral extraction for multi-gigahertz signal

Conference paper

On path-based learning and its applications in delay test and diagnosis

Conference paper

On using a 2-domain partitioned OBDD data structure in verification

Conference paper

Pattern selection for testing of deep sub-micron timing defects

Conference paper

Random jitter extraction technique in a multi-gigahertz signal

Conference paper

SSD tracking using dynamic template and Log-polar transformation

Conference paper

Static statistical timing analysis for latch-based pipeline designs

Conference paper

TranGen: A SAT-based ATPG for path-oriented transition faults

Conference paper

A Multimodal Image Database System

Article

An anatomy of a large-scale image search engine

Article

Critical Path Selection for Deep Sub-Micron Delay Test and Timing Validation

Article

DfT Sigma-Delta Modulator Architecture Implementation

Article

Enhanced Symbolic Simulation for Functional Verification of Embedded Array Systems

Article

Guest editors' introduction: Speed test and speed binning for complex ICs

Article

Modeling, testing, and analysis for delay defects and noise effects in deep submicron devices

Article

Practical considerations in applying Σ-Δ modulation-based analog BIST to sampled-data systems

Article

SHIVA – A Fast Hybrid Constraint Solver for Circuits

Article

Special Section on VLSI Design and CAD Algorithms-Timing Verification and Test Generation-Critical Path Selection for Deep Sub-Micron Delay Test and Timing Validation

Article

A circuit SAT solver with signal correlation guided learning

Conference paper

A comparison of BDDs, BMC, and sequential SAT for model checking

Conference paper

A signal correlation guided ATPG solver and its applications for solving difficult industrial cases

Conference paper

Delay defect diagnosis based upon a statistical timing model - The first step

Conference paper

Delay defect diagnosis based upon statistical timing models - The first step

Conference paper

Delta-sigma modulator based mixed-signal BIST architecture for SoC

Conference paper

Diagnosis of delay defects using statistical timing models

Conference paper

Diagnosis-Based Post-Silicon Timing Validation Using Statistical Tools and Methodologies

Conference paper

Enhancing diagnosis resolution for delay defects based upon statistical timing and statistical fault models

Conference paper

Experience in critical path selection for deep sub-micron delay test and timing validation

Conference paper

Multimedia web services for content filtering, searching, and digital rights management

Conference paper

On structural vs. functional testing for delay faults

Conference paper

SATORI - A fast sequential sat engine for circuits

Conference paper

Test consideration for nanometer scale CMOS circuits

Conference paper

The Confluence of Manufacturing Test and Design Validation

Conference paper

Using Logic Models to Predict the Detection Behavior of Statistical Timing Defects

Conference paper

Embedded software-based self-test for programmable core-based designs

Article

An Enhanced BIST Scheme for ADC and Non-monotonic DAC

Conference paper

Analysis of delay test effectiveness with a multiple-clock scheme

Conference paper

Combining ATPG and symbolic simulation for efficient validation of embedded array systems

Conference paper

Embedded Software-Based Self-Testing for SoC Design

Conference paper

Enhancing test efficiency for delay fault testing using multiple-clocked schemes

Conference paper

False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation

Conference paper

Hybrid learning schemes for multimedia information retrieval

Conference paper

MORF: A distributed multimodal information filtering system

Conference paper

On the development of ATPG based Satisfiability Checker

Conference paper

On theoretical and practical considerations of path selection for delay fault testing

Conference paper

On-chip analog response extraction with 1-bit Σ-Δ modulators

Conference paper

PBIR-MM: Multimodal image retrieval and annotation

Conference paper

Self-referential verification of gate-level implementations of arithmetic circuits

Conference paper

Self-testing second-order delta-sigma modulators using digital stimulus

Conference paper

Software-based weighted random testing for IP cores in bus-based programmable SoCs

Conference paper

Supporting subjective image queries without seeding requirements - Proposing test queries for Benchathlon

Conference paper

Testing second-order delta-sigma modulators using pseudo-random patterns

Conference paper

Limitations and challenges of computer-aided design technology for CMOS VLSI

Article

Pattern generation for delay testing and dynamic timing analysis considering power-supply noise effects

Article

Using word-level ATPG and modular arithmetic constraint-solving techniques for assertion property checking

Article

Vector generation for power supply noise estimation and verification of deep submicron designs

Article

Verifying sequential equivalence using ATPG techniques

Article

A self-test methodology for IP cores in bus-based programmable SoCs

Conference paper

An analysis of ATPG and SAT algorithms for formal verification

Conference paper

An on-chip short-time interval measurement technique for testing high-speed communication links

Conference paper

Delay testing considering crosstalk-induced effects

Conference paper

Embedded-software-based approach to testing crosstalk-induced faults at on-chip buses

Conference paper

Fast statistical timing analysis by probabilistic event propagation

Conference paper

HRM - A hierarchical simulator for full-chip power network reliability analysis

Conference paper

Induction-based gate-level verification of multipliers

Conference paper

Instruction-level DfT for testing processor and IP cores in system-on-a-chip

Conference paper

Mining image features for efficient query processing

Conference paper

PBIR - Perception-based image retrieval

Conference paper

PBIR: Perception-Based Image Retrieval-A system that can quickly capture subjective image query concepts

Conference paper

Support vector machine pairwise classifiers with error reduction for image classification

Conference paper

SVM binary classifier ensembles for image classification

Conference paper

AQUILA: An equivalence checking system for large sequential designs

Article

Estimation for maximum instantaneous current through supply lines for CMOS circuits

Article

Functionally testable path delay faults on a microprocessor

Article

On improving test quality of scan-based BIST

Article

Test point selection for analog fault diagnosis of unpowered circuit boards

Article

Testable path delay fault cover for sequential circuits

Article

A BIST scheme for on-chip ADC and DAC testing

Conference paper

A delta-sigma modulation based BIST scheme for mixed-signal systems

Conference paper

A sigma-delta modulation based BIST scheme for mixed-signal circuits

Conference paper

A testability metric for path delay faults and its application

Conference paper

An FPGA-based re-configurable functional tester for memory chips

Conference paper

Assertion checking by combined word-level ATPG and modular arithmetic constraint-solving techniques

Conference paper

Characterization of a pseudo-random testing technique for analog and mixed-signal built-in-self-test

Conference paper

Collaboration between industry and academia in test research

Conference paper

Dynamic timing analysis considering power supply noise effects

Conference paper

Efficient test mode selection and insertion for RTL-BIST

Conference paper

On testing the path delay faults of a microprocessor using its instruction set

Conference paper

Path selection and pattern generation for dynamic timing analysis considering power supply noise effects

Conference paper

Path selection for delay testing of deep sub-micron devices using statistical performance sensitivity analysis

Conference paper

Performance sensitivity analysis using statistical methods and its applications to delay testing

Conference paper

Static property checking using ATPG v.s. BDD techniques

Conference paper

Test challenges for deep sub-micron technologies

Conference paper

Test program synthesis for path delay faults in microprocessor cores

Conference paper

Testing and characterization of the one-bit first-order delta-sigma modulator for on-chip analog signal analysis

Conference paper

AutoFix: A hybrid tool for automatic logic rectification

Article

Current Directions in Automatic Test-Pattern Generation

Article

ErrorTracer: Design error diagnosis based on fault simulation techniques

Article

Fault emulation: A new methodology for fault grading

Article

Primitive delay faults: Identification, testing, and design for testability

Article

Test generation for linear time-invariant analog circuits

Article

A new bare die test methodology

Conference paper

Analysis of performance impact caused by power supply noise in deep submicron devices

Conference paper

Delay testing considering power supply noise effects

Conference paper

Improving the test quality for scan-based BIST using a general test application scheme

Conference paper

Specification back-propagation and its application to DC fault simulation for analog/mixed-signal circuits

Conference paper

Testing high speed VLSI devices using slower testers

Conference paper

VIP - an input pattern generator for identifying critical voltage drop for deep sub-micron designs

Conference paper

A hybrid methodology for switching activities estimation

Article

Efficient test-point selection for scan-based BIST

Article

Test-point insertion: scan paths through functional logic

Article

Delay Fault Testing for VLSI Circuits

Book

Algorithm for Verifying Retimed Circuits

Book chapter

AQUILA: A Local BDD-based Equivalence Verifier

Book chapter

Case Studies on Delay Testing

Book chapter

Conclusions and Future Work

Book chapter

Delay Fault Models

Book chapter

Delay Fault Simulation

Book chapter

Design for Delay Fault Testability

Book chapter

ErrorTracer: Error Diagnosis by Fault Simulation

Book chapter

Extension to Sequential Error Diagnosis

Book chapter

Incremental logic rectification

Book chapter

Incremental Verification for Combinational Circuits

Book chapter

Incremental Verification for Sequential Circuits

Book chapter

Introduction to Logic Debugging

Book chapter

Path Delay Fault Classification

Book chapter

RTL-to-Gate Verification

Book chapter

Symbolic Verification

Book chapter

Synthesis for Delay Fault Testability

Book chapter

Test Application Schemes for Testing Delay Defects

Book chapter

Test Generation for Path Delay Faults

Book chapter

A hybrid power model for RTL power estimation

Conference paper

An almost full-scan BIST solution - higher fault coverage and shorter test application time

Conference paper

Estimation of maximum power supply noise for deep sub-micron designs

Conference paper

Exact and approximate estimation for maximum instantaneous current of CMOS circuits

Conference paper

Fault-simulation based design error diagnosis for sequential circuits

Conference paper

Functional scan chain testing

Conference paper

LIBRA - a library-independent framework for post-layout performance optimization

Conference paper

National Science Foundation Workshop on future research directions in testing of electronic circuits and systems

Conference paper

Postlayout logic restructuring using alternative wires

Article

Pseudorandom testing for mixed-signal circuits

Article

Resynthesis of Combinational Circuits for Path Count Reduction and for Path Delay Fault Testability

Article

A Hybrid algorithm for test point selection for scan-based BIST

Conference paper

Analog fault diagnosis for unpowered circuit boards

Conference paper

AQUILA: An equivalence verifier for large sequential circuits

Conference paper

Design for primitive delay fault testability

Conference paper

ErrorTracer: A fault simulation-based approach to design error diagnosis

Conference paper

Estimation of maximum power and instantaneous current using a genetic algorithm

Conference paper

Fault macromodeling for analog/mixed-signal circuits

Conference paper

Incremental logic rectification

Conference paper

Post-layout logic restructuring for performance optimization

Conference paper

Test synthesis approach to reducing BALLAST DFT overhead

Conference paper

Vector generation for maximum instantaneous current through supply lines for CMOS circuits

Conference paper

Automatic generation of functionial vectors using the extended finite state machine model

Article

Classification and identification of nonrobust untestable path delay faults

Article

Design Validation: Formal Verification vs. Simulation vs. Functional Testing

Article

Fault macromodeling and a testing strategy for opamps

Article

Generation of high quality tests for robustly untestable path delay faults

Article

Perturb and simplify: multilevel boolean network optimizer

Article

Tutorial and Survey Paper: Gate-Level test generation for sequential circuits

Article

An ATPG-based framework for verifying sequential equivalence

Conference paper

An Efficient compact test generator for IDDQ testing

Conference paper

Built-In Self Test for Analog and Mixed-Signal Designs

Conference paper

Compact vector generation for accurate power simulation

Conference paper

Driving toward higher IDDQ test quality for sequential circuits: A generalized fault model and its ATPG

Conference paper

Error correction based on verification techniques

Conference paper

Identification and test generation for primitive faults

Conference paper

Implicit functional testing for analog circuits

Conference paper

New hybrid methodology for power estimation

Conference paper

Novel methodology for transistor-level power estimation

Conference paper

On verifying the correctness of retimed circuits

Conference paper

Scan paths through functional logic

Conference paper

Test point insertion: Scan paths through combinational logic

Conference paper

Testable path delay fault cover for sequential circuits

Conference paper

Single-Clock Partial Scan

Article

Test synthesis: the practicality of DFT

Article

Timing-Driven Partial Scan

Article

An Efficient algorithm for local don't care sets calculation

Conference paper

Fast identification of robust dependent path delay faults

Conference paper

Fault emulation: A new approach to fault grading

Conference paper

Generation of high quality tests for functional sensitizable paths

Conference paper

Logic optimization by an improved sequential redundancy addition and removal technique

Conference paper

Logic synthesis for engineering change

Conference paper

Minimax end-to-end delay routing and capacity assignment for virtual circuit networks

Conference paper

Partial scan designs without using a separate scan clock

Conference paper

Pseudo-random testing and signature analysis for mixed-signal circuits

Conference paper

Speeding up power estimation by topological analysis

Conference paper

Timing-driven test point insertion for full-scan and partial-scan BIST

Conference paper

Automatic test generation for digital electronic circuits

Article

Comprehensive fault macromodel for opamps

Conference paper

Generation of high quality non-robust tests for path delay faults

Conference paper

Layout driven logic synthesis for FPGAs

Conference paper

On the computation of the set of reachable states of hybrid models

Conference paper

On the joint virtual path assignment and virtual circuit routing problem in ATM networks

Conference paper

Test Synthesis in Cooperation with the International Test Conference

Conference paper

Delay-Fault Test Generation and Synthesis for Testability Under a Standard Scan Design Methodology

Article

On the over-specification problem in sequential ATPG algorithms

Article

Redundancy Removal for Sequential Circuits Without Reset States

Article

STOIC: State Assignment Based on Output/Input Functions

Article

Transition Fault Testing for Sequential Circuits

Article

Automatic functional test generation using the extended finite state machine model

Conference paper

Delay testing for non-robust untestable circuits

Conference paper

Multi-chip Modules Introduction

Conference paper

Multi-level logic optimization by redundancy addition and removal

Conference paper

Sequential logic optimization by redundancy addition and removal

Conference paper

Virtual path assignment and virtual circuit routing in ATM networks

Conference paper

A Functional Fault Model for Sequential Machines

Article

Initializability Consideration in Sequential Machine Synthesis

Article

A partial enhanced-scan approach to robust delay-fault test generation for sequential circuits

Conference paper

An ATPG-based approach to sequential logic optimization

Conference paper

On the over-specification problem in sequential ATPG algorithms

Conference paper

State assignment using input/output functions

Conference paper

Test generation for delay faults in non-scan and partial scan sequential circuits

Conference paper

Timing-driven partial scan

Conference paper

Transition fault simulation for sequential circuits

Conference paper

Methods for synthesizing testable sequential circuits

Article

Behavioral and logic synthesis for performance and testability

Conference paper

On removing redundancy in sequential circuits

Conference paper

Pascant: A partial scan and test generation system

Conference paper

Robust delay-fault test generation and synthesis for testability under a standard scan design methodology

Conference paper

Test function specification in synthesis

Conference paper

A Partial Scan Method for Sequential Circuits with Feedback

Article

A Simulation-Based Method for Generating Tests for Sequential Circuits

Article

Finite state machine synthesis with embedded test function

Article

A single-state-transition fault model for sequential machines

Conference paper

An architecture for synthesis of testable finite state machines

Conference paper

An entropy measure for the complexity of multi-output Boolean functions

Conference paper

Functional test generation for finite state machines

Conference paper

Synthesis of testable finite state machines

Conference paper

Timing optimization with testability considerations

Conference paper

A Directed Search Method for Test Generation Using a Concurrent Simulator

Article

Unified Methods for VLSI Simulation and Test Generation

Book

Concurrent test generation and design for testability

Conference paper

Design of sequential machines for efficient test generation

Conference paper

Economical scan design for sequential logic test generation

Conference paper

Fault simulation in a pipelined multiprocessor system

Conference paper

State assignment for initializable synthesis

Conference paper