An Efficient 6TP SRAM-Based CIM Macro With Column ADCs for Binarized Neural Networks

Bioinspired In-Sensor Multimodal Fusion for Enhanced Spatial and Spatiotemporal Association

Ultraflexible Monolithic Three-Dimensional Static Random Access Memory

An End-to-End Deep-Learning-Based Indirect Time-of-Flight Image Signal Processor

Enhanced Reliability of Ultra-low-k Dielectric with Columnar Pores Using hBN Capping Layer

Stacked Complementary Field-Effect Transistors: Promises and Challenges

3-Masks-Processed Sub-100 nm Amorphous InGaZnO Thin-Film Transistors for Monolithic 3D Capacitor-Less Dynamic Random Access Memories

A CMOS-Compatible Gate-Assisted Photonic Demodulator With Contrast Enhancement for Time-of-Flight Sensing

Computational event-driven vision sensors for in-sensor spiking neural networks

Deep Sub-Micron Self-Aligned Bottom-Gate Amorphous InGaZnO Thin-Film Transistors With Low-Resistance Source/Drain

Generic Compact Modeling of Emerging Memories with Recurrent NARX Network

Intercoupling of Cascaded Metasurfaces for Broadband Spectral Scalability

Near-Ideal Top-Gate Controllability of InGaZnO Thin-Film Transistors by Suppressing Interface Defects with an Ultrathin Atomic Layer Deposited Gate Insulator

Polarization-multiplexed metaholograms with erasable functionality

Sub-100 nm Self-Aligned Top-Gate Amorphous InGaZnO Thin-Film Transistors With Gate Insulator of 4 nm Atomic-Layer-Deposited AlO_x

Threshold Voltage Model for 2-D FETs With Undoped Body and Gated Source

Ultra-Flexible Monolithic Three-Dimensional Complementary Metal-Oxide-Semiconductor Electronics

Ultra-thin gate insulator of atomic-layer-deposited AlO_x and HfO_xfor amorphous InGaZnO thin-film transistors

Ultra-thin top-gate insulator of atomic-layer-deposited HfO_x for amorphous InGaZnO thin-film transistors

A High Sensitivity and Modulation Contrast Photonic Demodulator for Time-of-Flight Application

A Multiple Junction Photonic Demodulator with Low Power Consumption for Time-of-Flight Application

Complementary Field-Effect Transistors: From Silicon to 2D Materials

Design and Demonstration of Cu/ Al₂O₃ /Cu RRAM with Complementary Resistance Switching Characteristic

Generic Memory Modeling with Recurrent Neural Network

Improved Split C–V Technique for Effective Mobility Extraction in Self-Aligned Top-Gate Amorphous InGaZnO TFTs with Short Channel

Sub-Micron Oxide TFT for the Era of Oxide-Based Display

A CMOS-Compatible Photonic Demodulator With Low-Power Consumption for Time-of-Flight Image Sensor

A neuromorphic core based on threshold switching memristor with asynchronous address event representation circuits

Analysis of Carrier Behavior for Amorphous Indium Gallium Zinc Oxide After Supercritical Carbon Dioxide Treatment

Fabrication and properties of nanoencapsulated stearic acid phase change materials with Ag shell for solar energy storage

High-Performance Self-Aligned Top-Gate Amorphous InGaZnO TFTs With 4 nm-Thick Atomic-Layer-Deposited AlO_x Insulator

On-Chip Integrated High Gain Complementary MoS₂ Inverter Circuit with Exceptional High Hole Current P-Channel Field-Effect Transistors

Tunable stretchable strain sensors enabled by patterned Ecoflex-vertical aligned carbon nanotube arrays and pre-stretching transfer

A CMOS Compatible In-sensor Computing Neural Network with Gate/Body-Tied PMOSFET Array

Analysis of the Wave Modes for Super-High Frequency SAW Devices on the SiO₂/IDT/LiNbO₃Structure

Compact Modeling of Phase Change Memory with Parameter Extractions

Hollow Airgap Technology for CMOS Maximum Interconnect Capacitance Reduction

Low-loss RF passive elements by top-metal air-gap technology

Use of Online In-Class Quizzes to Motivate and Engage Students in Courses on Semiconductor Devices and Integrated Circuits

A flexible high quality-factor bulk acoustic resonator enabled with transferred single-crystal piezoelectric thin film for sensing applications

A Modified NMOS Inverter with Rail-To-Rail Output Swing and Its Application in the Gate Driver Integrated by Metal Oxide TFTs

A Robust and Efficient Compact Model for Phase-Change Memory Circuit Simulations

Air-Gap Technology with a Large Void-Fraction for Global Interconnect Delay Reduction

Complementary Two-Dimensional (2-D) FET Technology with MoS₂/hBN/Graphene Stack

High Current Nb-Doped P-Channel MoS₂ Field-Effect Transistor Using Pt Contact

High Q Lateral-field-excited Bulk Resonator Based on Single-crystal LiTaO₃ for 5G Wireless Communication

Hybrid memristor-CMOS neurons for in-situ learning in fully hardware memristive spiking neural networks

Low-Temperature Grown Vertically Aligned Carbon Nanotube Array for an Optimal Infrared Bolometer

Transferred Metal Gate to 2D Semiconductors for Sub-1V Operation and Near Ideal Subthreshold Slope

A Full-region Model For Ultra-Scaled MoS₂ MOSFET Covering Direct Source-Drain Tunneling

Animated MOOC Videos on Semiconductor Devices and Their Versatile Use for Self-Learning & Formal Teaching Delivery

CMOS-Compatible Time-of-Flight 3D Imaging Sensors and Systems

Complementary Two-Dimensional (2-D) MoS₂ FET Technology

A Compact Phase Change Memory Model with Dynamic State Variables

A SPICE Model of Phase Change Memory for Neuromorphic Circuits

Analytical Monolayer MoS₂ MOSFET Modeling Verified by First Principle Simulations

Bistable active spectral tuning of one-dimensional nanophotonic crystal by phase change

Increasing threshold voltage and reducing leakage of AlGaN/GaN HEMTs using dual-layer SiNx stressors

Low-Power Complementary Inverter with Negative Capacitance 2D Semiconductor Transistors

Phase change induced active metasurface devices for dynamic wavefront control

Physical Model of Current-Assisted Photonic Demodulator (CAPD) for Time-of-Flight CMOS Image Sensor

Quasi-Normally-Off AlGaN/GaN HEMTs with SiN Stress Liner and Comb Gate for Power Electronics Applications

Self-driven WSe₂ photodetectors enabled with asymmetrical van der Waals contact interfaces

Sensing-range-tunable pressure sensors realized by self-patterned-spacer design and vertical CNT arrays embedded in PDMS

Synthesis of Vertical Carbon Nanotube Interconnect Structures Using CMOS-Compatible Catalysts

Ultralow-k Dielectric With Structured Pores for Interconnect Delay Reduction

Teaching Embedded System Design Among K-12 Students Based on Trees-Forest-View Methodology

Design Considerations for Current-Assisted Photonic Demodulator (CAPD) in Time-of-Flight CMOS Image Sensor

High Frequency Monolithic Inductor with Air-Gaps

Interconnect Structures for Reducing Intra-Layer Metal-to-Metal Capacitances

Mechanically Stable Ultra-Low-k Dielectric and Air-gap Technology

Memory Modeling for Neuromorphic Computing

Memory Modeling with Dynamic Time Evolution Method for Neuromorphic Circuit Simulations

Quasi-Normally-Off AlGaN/GaN HEMTs with Strained Comb Gate for Power Electronics Applications

A Dynamic Time Evolution Method for Concurrent Device-Circuit Aging Simulations

Control of Hexagonal Boron Nitride Dielectric Thickness by Single Layer Etching

Interconnect Technology With h-BN-Capped Air-Gaps

Low Temperature Synthesis of High-Density Carbon Nanotubes on Insulating Substrate

Modeling Current-Voltage Characteristics of Bilayer Organic Light-Emitting Diodes

Phase Change Memory Cell With Reconfigured Electrode for Lower RESET Voltage

Polycrystalline transistor with multiple thresholds

Design of Current-Assisted Photonic Demodulator (CAPD) for Time-of-Flight CMOS Image Sensor

Enhancing IGZO Thin Film Transistor Scalability Through Tunneling Contact

High Performance MoS2 N-Channel MOSFETs

High Performance MoS2 N-Channel MOSFFTs

Improving the drive current of AlGaN/GaN HEMT using external strain engineering

Integration of Carbon Nanotube as Via Contact to MoS2

Modeling the Heating Effects in PCM for Circuit Simulation Accelerations

Revisiting the Crystallization Model of Phase Change Memory with Ab Initio Simulatons

Silicon Nitride Stress Liner Impacts on the Electrical Characteristics of AlGaN/GaN HEMTs

Steep Slope p-type 2D WSe₂ Field-Effect Transistors with Van der Waals Contact and Negative Capacitance

Terahertz broadband band-stop filter based on metasurface

Circular Electrodes to Reduce the Current Variation of OTFTS With the Drop-casted Semiconducting Layer

Contact Resistance Reduction of Carbon Nanotube via through O₂ Plasma Post-Synthesis Treatment

High-resolution flexible AMOLED display integrating gate driver by metal-oxide TFTs

On the Formulation of Self-Heating Models for Circuit Simulation

On-Demand Band-Rejected Wideband Antenna Based on Peelable Resonator Membrane

Origin of Nonideal Graphene-Silicon Schottky Junction

Prototyping of Terahertz Metasurface by One-Step Lithographically Defined Templating

Self-Driven Metal–Semiconductor–Metal WSe2 Photodetector with Asymmetric Contact Geometries

同质结隧穿场效应晶体管 and 异质结隧穿场效应晶体管

A Smooth and Continuous Phase Change Memory SPICE Model for Improved Convergence

An effective mobility model for tunneling double-gate MOSFET (T-FinFET)

Band-rejected Wideband Antenna Based on Peelable Resonator Membrane

Carbon Enhanced BEOL Technology

Carrier Injection Mechanism of Metal-MoS₂ Ohmic Contact in MoS₂ FETs

CMOS Technology with Integrated Carbon-Nanotube Contact Plugs

Compact Models for Giga-Scale Memory System

Current Conduction Mechanisms in h-BN as a Dielectric Material

Current Enhancement of Graphene-Inserted Tunneling Contact IGZO TFT

Engineering of Graphene-to-Semiconductor Contacts

i-MOS: a Cloud-based Circuit Simulation and Compact Modeling Platform

Impact of CNT Diameter Distribution on CNT filled Via Scaling

Synthesis of Carbon Nanotube in Sub-100nm Vias on Ni Silicide

Ultra-Low-k Interlayer Dielectric for Post-Moore CMOS Interconnect

A 1.2V-to-0.4V 3.2GHz-to-14.3MHz Power-Efficient 3-Port Register File in 65-nm CMOS

A 140mV Variation-Tolerant Deep Sub-Threshold SRAM in 65nm CMOS

A Low-Power Ring Oscillator Using Pull-Up Control Scheme Integrated by Metal-Oxide TFTs

Artificial Neural Network Design for Compact Modeling of Generic Transistors

Doping of Two-dimensional MoS₂ by High Energy Ion Implantation

Exchange bias study of sub-100 nm-diameter CoFeB/IrMn antidot and nanodot arrays fabricated by nanosphere lithography

High-Current Drivability Fibonacci Charge Pump With Connect-Point-Shift Enhancement

Low Frequency Behavior of CVD Graphene from DC to 40 GHz

Low Power Phase Change Memory With Vertical Carbon Nanotube Electrode

Numerical Study on Random Dopant Fluctuation Effects on T-FinFET Performance

Reduced Magnetic Coercivity and Switching Field in NiFeCuMo/Ru/NiFeCuMo Synthetic-ferrimagnetic Nanodots

Synthesis and Interface Characterization of CNTs on Graphene

Tunneling Contact IGZO TFTs with Reduced Saturation Voltages

Silicon-Based Junctionless MOSFETs: Device Physics, Performance Boosters and Variations

A Design Methodology of Efficient On-Chip Wireless Power Transmission

A Universal Approach for Signal Dependent Circuit Reliability Simulation

A Voltage-Scalable Zero-Delay-Overhead Scheme for Standby Power Reduction in Dynamic Register Files

BEOL Technology for Heterogeneous System Integration

Catalyst Design for High-Density and Low-Temperature CNT Synthesis on Conductive Ti Silicide Substrate

Concurrent Device/circuit Aging for General Reliability Simulations

Design Considerations for Mechanically Stable Air-Gap Interconnect

Gate-Controlled Electron Injection in Tunneling Contact IGZO TFTs

Modeling of Fringe Current for Semiconductor-Extended Organic TFTs

Ohmic Contact Formation Between Ge₂Sb₂Te₅ Phase Change Material and Vertically Aligned Carbon Nanotubes

Temperature Compensated Super-High-Frequency (2-8 GHz) Surface Acoustic Wave Devices

A 200-Channel Area-Power-Efficient Chemical and Electrical Dual-Mode Acquisition IC for the Study of Neurodegenerative Diseases

A Compact Low-Power 4-Port Register File with Grounded Write Bitlines and Single-Ended Read Operations

A Compact Model for Double-Gate Heterojunction Tunnel FETs

A High Conversion Ratio Component-Efficient Charge Pump for Display Drivers

A High-Voltage (> 600 V) N-Island LDMOS With Step-Doped Drift Region in Partial SOI Technology

A physics based analytic model for gate all around MOSFETs with SiO₂-Core Si-shell architecture

A Short Channel Double-gate Junctionless Transistor Model Including the Dynamic Channel Boundary Effect

Analytical Current Model for Long-Channel Junctionless Double-Gate MOSFETs

Carbon Nanotube Contact Plug on Silicide for CMOS Compatible Interconnect

Carrier Type Control of WSe₂ Field-Effect Transistors by Thickness Modulation and MoO₃ Layer Doping

Depth-of-Focus Determination for Talbot Lithography of Large-Scale Free-Standing Periodic Features

Doping Enhanced Barrier Lowering in Graphene-Silicon Junctions

Effect of Near-Field Diffraction in Photolithography of Hexagonal Arrays for Dichroic Filters

Field-Angle and DC-Bias Dependence of Spin-Torque Diode in Giant Magnetoresistive Microstripe

Metal-Oxide-Semiconductor Field-Effect Transistor Resonant Detection on Terahertz Radiation in Optical Exciting Regime

Modeling CNTFET Performance Variation due to Spatial Distribution of Carbon Nanotubes

Ultralow-k Dielectric With Nanotubes Assisted Vertically Aligned Cylindrical Pores

Universal framework for temperature dependence prediction of the negative bias temperature instability based on microscope pictures

Tunneling Field Effect Transistor Technology

Compact Models of TFETs

Steep Slope Devices and TFETs

A Sustainable Strategy of Farming in Radioactive Contaminated Farmland: A Case Study in Fukushima

Applications of Carbon-Nanotubes in CMOS Interconnect Technology Enhancement

Breakdown Mechanism of Horizontally Aligned Carbon Nanotube (CNT)

Carbon Nanotube Assisted Interconnect Technology

Carbon Nanotube Enhanced CMOS Interconnect

Dynamic NBTI Simulation Coupling with Self-Heating Effect in SOI MOSFETs

Exchange Bias Study of CoFeB/IrMn Antidot and Nanodot Arrays Fabricated by Nanosphere Lithography

Fabrication and Measurement of Millimeter-Wave On-chip MIMO Antenna for CMOS RFIC's

Fully Transparent Solution-Processed Carbon Nanotube Thin Film Transistors On a Flexible Substrate

Modeling Current Reduction for PCM Cell with Thermal Buffer Layer

Modeling of Planar Spreading of Current for OTFT of Low Aspect Ratio

Modeling spatial distribution induced variability in CNT array based FETs

Patterning CNT-forest for the Fabrication of Nano-Channel OFET of High W/L

Reduced Magnetic Coercivity and Switching Field in Conetic-Alloy-Based Synthetic-Ferrimagnetic Nanodots

Reliability-aware Device Compact Modeling and Implications On Circuit Aging Simulations

Study Progress on FET-based Terahertz Wave Generation and Detection

Characterization of interface trap dynamics responsible for hysteresis in organic thin-film transistors

Comparative Analysis of Carrier Statistics on MOSFET and Tunneling FET Characteristics

Eight-FinFET Fully Differential SRAM Cell With Enhanced Read and Write Voltage Margins

Extraction and modeling of layout-dependent MOSFET gate-to-source/drain fringing capacitance in 40 nm technology

Flexible structured high-frequency film bulk acoustic resonator for flexible wireless electronics

Gate Capacitance Model for Aligned Carbon Nanotube FETs With Arbitrary CNT Spacing

Low voltage and high ON/OFF ratio field-effect transistors based on CVD MoS2 and ultra high-k gate dielectric PZT

Resistance Determination for Sub-100-nm Carbon Nanotube Vias

Self-aligned offset gate poly-Si TFTs using photoresist trimming technology

SRAM precharge system for reducing write power

Suppression of subthreshold characteristics variation for junctionless multigate transistors using high-k spacers

Analytic High Frequency Model of SOI-MOSFETs with Active Transmission Line Analysis

A 50-Ohm Semi-enclosed Stripline Design in a 90nm CMOS Process for 60-GHz Millimeter- Wave Integrated Circuits

A 65nm 3.2GHz 44.2mW Low-Vt Register File with Robust Low-capacitance Dynamic Local Bitlines

All-Carbon Interconnect: Fabrication and Integration

An Area-Efficient 1.5-GHz Dual-V_DD 4-Port Register File for Real-Time Microprocessors

Compact Transmission Line Design in a Multi-Metallization Nano-CMOS Process for Millimeter-Wave Integrated Circuits

Efficient On-Chip Wireless Power Transmission

Efficient wireless power transmission technology based on above-CMOS integrated (ACI) high quality inductors

Improved Electrical Stability of Double-gate a-IGZO TFTs

Interface Engineering to Enhance Phase Change Memory Programmability

Investigation of Nitrogen Enhanced NBTI Effect Using the Universal Prediction Model

Modeling active dimension for phase change memory cell

Modeling of On-Chip Wireless Power Transmission System

Nanoscale Register File Circuit Design – Challenges and Opportunities

Write Ability Enhancement Techniques for L1 Cache on Next-Generation IBM POWER^TM Processors

3-D Resistance Model for Phase-Change Memory Cell

A Hybrid a-Si and Poly-Si TFTs Technology for AMOLED Pixel Circuits

An Analytic Model for Gate-all-around Silicon Nanowire Tunneling Field Effect Transistors

Analytical Modeling of Capacitances for GaN HEMTs, Including Parasitic Components

Highly Aligned Graphene/Polymer Nanocomposites with Excellent Dielectric Properties for High Performance Electromagnetic Interference Shielding

Implementation of Fully Self-Aligned Homojunction Double-Gate a-IGZO TFTs

Model Order Reduction for Quantum Transport Simulation of Band-To-Band Tunneling Devices

Modeling of Mutual Coupling Between Planar Inductors in Wireless Power Applications

SPICE Modeling of Double-Gate Tunnel-FETs Including Channel Transports

A Channel Potential Based Model for SiO2- Core Si-Shell SRGMOSFET

A gate leakage model for double gate tunneling field-effect transistors

A Low-noise Local Bitline Technique for Dual-Vt Register Files

A new degradation mechanism and its role on negative bias temperature instability in metal-oxide-semiconductor devices

A novel Makowski charge pump and its optimization using Lagrange theorem

A physics based Potential Model for Cylindrical Surrounding Gate MOSFETs with SiO₂-core Si-Shell Structure

A Web-based Education Platform for Nanoscale Device Modeling and Circuit Simulation

An Analytic Model for Nanowire Tunnel-FETs

An Analytic Potential Based Model for Gate-all-around Nanowire Tunnel-FETs

Analytical model of the subthreshold behavior in short-channel junctionless cylindrical surrounding-gate mosfets

Analytical Modeling for AlGaN/GaN HEMTs

Atomic disorder scattering in emerging transistors by parameter-free first principle modeling

Atomistic Simulation of Phase Change Memory During Switching

Bias stress induced threshold voltage instability in solution processed organic thin film transistor

Characteristics of double-gate a-IGZO TFT

Compact modeling beyond device physics

Critical parasitic capacitance in nano-scale phase-change memory (PCM) cell

Developing a common compact modeling platform for model developers and users

Developing a Common Compact Modeling Platform for Model Developers and Users

Developing i-MOS as a Compact Model Standardization Platform

Double-gate tunneling FET with asymmetric gate structure and pocket source

Fabrication and characterization of carbon nanotube interconnect vias for next-generation technology nodes

Impact of Lateral Fin-Width Non-Uniformity of FinFETs

Influence of fin-width lateral variations of a FinFET

Low Voltage SRAM Design using Tunneling Regime of CNTFET

Metal-gate resistance with skin effect consideration in nanoscale MOSFETs for millimeter-wave ICs

Multi-walled carbon nanotube coated microelectrode array for high-throughput, sensitive dopamine detection

Powering the More than Moore Electronics with i-MOS

Research progress on core-shell nanowire FETs

Silicon nanowire metal-oxide-semiconductor field effect transistor NBTI effect modeling and application in circuit performance simulation

Standardizing the Compact Model Developments for Emerging Transistors

Study on nucleation characteristic of phase change memory set operation using numerical simulation

The pathway to develop an industrial standard device model: From device physics to parameter extraction

Using 0-dimensional silica to control diameter and density of carbon nanotubes

A Comparative Study of Ballistic Transport Models for Nanowire MOSFETs

A Nonlinear Poisson-Schrodinger Solver Under Cylindrical Coordinate for Quantum Effect in Nanowire MOSFET

Design and Verification of a High Performance LED Driver with an Efficient Current Sensing Architecture

Effects of Fin Sidewall Angle on Subthreshold Characteristics of Junctionless Multigate Transistors

First Principles Simulations of Nanoscale Silicon Devices With Uniaxial Strain

Non-Charge-Sheet Analytic Model for Ideal Retrograde Doping MOSFETs

Numerical Electron Mobility Model of Nanoscale Symmetric, Asymmetric and Independent Double-Gate MOSFETs

Silicon-Embedded Receiving Coil for High-Efficiency Wireless Power Transfer to Implantable Biomedical ICs

Suppression of tunneling leakage current in junctionless nanowire transistors

Surface acoustic wave resonators based on (002) AlN/Pt/diamond/silicon layered structure

Temperature-compensated high-frequency surface acoustic wave device

Visible-light photoresponse of AlN-based film bulk acoustic wave resonator

Modeling FinFETs for CMOS Applications

Nanoscale Semiconductor Memories Technology and Applications: Chapter 10. Phase-Change Memory Cell Model and Simulation

A 51fA/Hz0.5 Low Power Heterodyne Impedance Analyzer for Electrochemical Impedance Spectroscopy

A DC Model of TFETs for SPICE Simulation

Application of Multi-frequency Test and Neural Network to Fault Diagnosis in Analog Circuits

Effect of Parasitic Capacitances and Resistances on the RF Performance of Nanoscale MOSFETs

First Principle Simulations of the [110] Uniaxial Strain Effects in Electron Transport

Integration of Diamond-like Carbon and AlN for Acoustic Wave Devices

Modeling of an Inductive Link for Wireless Power Applications

Multi-frequency Test for Analog Circuits

Numerical study on effects of random dopant fluctuation in double gate tunneling FET

Numerical study on gate-All-Around tunneling FET with SiO2 core and Si shell structure

Numerical Study on Nanowire Tunnel FET with Dynamic Threshold Operation Architecture

Predicting Key Parameters of Inductive Power Links

Random Dopant Fluctuation Effects on Double Gate Tunneling FET Performance

Strain Modeling in Source Exhaustion Regime of Carbon Nanotube Field Effect Transistor

Study on Dynamic Threshold Nanowire Tunneling FET

32.9 nV/rt Hz-60.6 dB THD Dual-Band Micro-Electrode Array Signal Acquisition IC

A Compact CMOS Compatible Oxide Antifuse With Polysilicon Diode Driver

A Junctionless Nanowire Transistor With a Dual-Material Gate

A unified charge-based model for SOI MOSFETs applicable from intrinsic to heavily doped channel

An Analytical Charge Model for Double-Gate Tunnel FETs

An Explicit Surface Potential Model of Bulk-MOSFETs with Inclusion of Poly-Gate Accumulation, Depletion and Inversion Effects

Gate underlap design for short channel effects control in cylindrical gate-all-around MOSFETs based on an analytical model

Low-Temperature ZnO TFTs Fabricated by Reactive Sputtering of Metallic Zinc Target

Model-Based Prediction of the Plasma Oscillation Excitation Response Characteristics of a High-Electron Mobility Transistor-Based Terahertz Photomixer with the Cap Region

Modeling of the Cell-Electrode Interface Noise for Microelectrode Arrays

One-time-programmable memory in LTPS TFT technology with metal-induced lateral crystallization

Phase-change memory with multifin thin-film-transistor driver technology

Polynomial-Effective-Channel-Mobility-Based Above-Threshold Current Model for Undoped Polycrystalline-Silicon Thin-Film Transistors Consistent With Pao-Sah Model

Reactive Radiofrequency Sputtering-Deposited Nanocrystalline ZnO Thin-Film Transistors

The Use of SU-8 Topographically Guided Microelectrode Array in Measuring Extracellular Field Potential Propagation

Unified Scale Length for Four-Terminal Double-Gate MOSFETs

A charge based non-quasi-static transient model for SOI MOSFETs

A Compact Model for Double-Gate Tunneling Field-Effect-Transistors and Its Implications on Circuit Behaviors

A MATLAB Program for Volterra Distortion Analysis in CMOS Switched Source Follower

An experimental study of Engineering-Science-Mathematics Approach in elementary engineering and science education

Analytical Drain Current Model for Organic Thin-Film Transistors

Building a user friendly infrastructure for compact model development in the nano-device era

Comparison of MEA signals derived from peritoneal mast cells and RBL-2H3 cells

Fault Diagnosis of Analog Circuits Based on Multi-frequency Test and Neural Network Method

Field-Based 3D Capacitance Modeling for sub-45-nm On-Chip Interconnect

Field-Based Parasitic Capacitance Models for 2D and 3D sub-45-nm Interconnect

Geometry based resistance model for phase change memory

i-MOS: A platform for compact model sharing

Investigations of fin vertical nonuniformity effects on junctionless multigate transistor

Modeling of mutual inductance for planar inductors used in inductive link applications

Numerical Study on Dual Material Gate Nanowire Tunnel Field-Effect Transistor

Reduction of ambipolarity in carbon nanotube field-effect transistor by non-uniform source/drain doping and increased extension length

Simulation on Random Dopant Fluctuation Effect Impact on Double Gate MOSFET and Corresponding 6-T SRAM Performance

Wireless power link design using silicon-embedded inductors for brain-machine interface

3-D Numerical Simulation Study on 20 nm NMOSFET Design

A rigorous and concise surface potential-based core model for the undoped symmetric double-gate metal-oxide-semiconductor field effect transistors

Cardioprotective Effects of Potassium Channel Openers on Rat Atria and Isolated Hearts under Acute Hypoxia

Computation Efficient Yet Accurate Surface Potential Based Analytic Model for Symmetric DG MOSFETs to Predict Current-Voltage Characteristics

Driving Device Comparison for Phase-Change Memory

Highly accurate dual-band cellular field potential acquisition for brain-machine interface

Modeling Short-Channel Effect of Elliptical Gate-All-Around MOSFET by Effective Radius

Phase-Change Memory RESET Model Based on Detailed Cell Cooling Profile

The Significance of Chloride in the Inhibitory Action of Disodium Cromoglycate on Immunologically-stimulated Rat Peritoneal Mast Cells

Uniaxial Strain Effects on Electron Ballistic Transport in Gate-All-Around Silicon Nanowire MOSFETs

Zero-Mask Contact Fuse for One-Time-Programmable Memory in Standard CMOS Processes

A 38.6nV/Hz(0.5)-59.6dB THD Dual-Band Micro-Electrode Array Signal Acquisition IC

A phase-change random access memory model for circuit simulation

A Unified Drain Current Model for Nanoscale Double-Gate and Surrounding-Gate MOSFETs Incorporating Velocity Saturation

An Oxide/Silicon Core/Shell Nanowire FET

Comparison and insight into long-channel MOSFET drain current models

Cross-Section Control of Stacked Nanowires Formed by Bosch Process and Oxidation

i-MOS.org - interactive Modeling and Online Simulation platform for compact modeling

Nonparabolicity effects of the ultra-thin body double-gate MOSFETs

Phase-change memory on thin-film-transistor technology

Predicting Key Features of Double-Gate Tunnel FETs

Vertical Non-uniformity Effect on FinFET Performance Characteristics

A generic numerical model for detection of terahertz radiation in MOS field-effect transistors

A noncharge-sheet channel potential and drain current model for dynamic-depletion silicon-on-insulator metal-oxide-semiconductor field-effect transistors

A Study of the Relationship Between Pharmacologic Preconditioning and Adenosine Triphosphate-Sensitive Potassium (K-ATP) Channels on Cultured Cardiomyocytes Using the Microelectrode Array

A system-on-chip EPC Gen-2 passive UHF RFID tag with embedded temperature sensor

Analytical solution of subthreshold channel potential of gate underlap cylindrical gate-all-around MOSFET

Charge-based model for symmetric double-gate MOSFETs with inclusion of channel doping effect

Comparison of electrical stress-induced charge carrier generation/trapping and related degradation of SiO 2 and HfO 2/SiO 2 gate dielectric stacks

Continuous surface potential versus voltage equation of intrinsic surrounding-gate MOSFETs and analytic solution from accumulation to strong inversion region

Diode parameter extraction by a linear cofactor difference operation method

Generic Compact Model of Double-Gate MOSFETs Applicable to Different Operation Modes and Channels

Introduction to the Special Section on Electronic and Ionic Interfaces to Biomolecules and Cells

Numerical Simulation of Detection Response of Field Effect MOS Transistor to Modulated Terahertz Radiation Signal

Silicon-based nanowire MOSFETs: from process and device physics to simulation and modeling

3-D matrix nano-wire transistor fabrication on silicon substrate

A high power switch-mode LED driver with an efficient current sensing scheme

A Potential-based Analytic Model for Monocrystalline Silicon Thin-film Transistors on Glass Substrates

A system-on-chip EPC Gen-2 passive UHF RFID tag with embedded temperature sensor

A Unified Drain Current Model for Nanoscale Double-Gate and Surrounding-Gate MOSFETs Incorporating Velocity Saturation

Analytical subthreshold channel potential model of asymmetric gate underlap gate-all-around MOSFET

Bandstructures of Unstrained and Strained Silicon Nanowire

Characteristics of subband current ratio in double-gate MOSFET

Correlation between gated-diode R-G current and performance degradation of SOI n-MOSFETs after F-N stress test

Cross-section control of stacked nanowires formed by bosch process and oxidation

Determination of unidirectional field potential propagation using MEA chips with topographical guidance

RESET modeling of PCM using thermal budget approach

Submicron MILC TFT performance enhancement by crystallization after patterning

The impact of device parameter variation on double gate tunneling FET and double gate MOSFET

To Characterise The Membrane Field Potential Changes Following Non-Immunological and Immunological Activations Of Rat Peritoneal Mast Cells

Two-transistor active pixel image sensor with active diode reset

A charge-based compact model for predicting the current-voltage and capacitance-voltage characteristics of heavily doped cylindrical surrounding-gate MOSFETs

A complete analytic surface potential-based core model for intrinsic nanowire surrounding-gate MOSFETs

A continuous surface-potential solution from accumulation to inversion for intrinsic symmetric double-gate MOSFETs

A multi-stage low-dropout regulator with 1 pF compensation capacitor for System-on-Chip applications

A surface potential-based non-charge-sheet core model for undoped surrounding-gate MOSFETs

Effects of body doping on threshold voltage and channel potential of symmetric DG MOSFETs with continuous solution from accumulation to strong-inversion regions

Electrical stress-induced charge carrier generation/trapping related degradation of HfAlO/SiO2 and HfO2/SiO2 gate dielectric stacks

Mechanism of positive charge generation in the bulk of HfAlO/SiO2 stack

Modulatory action of potassium channel openers on field potential and histamine release from rat peritoneal mast cells

Sub-threshold behavior of long channel undoped cylindrical surrounding-gate MOSFETs

Terahertz Wave Generation and Detection Analysis of Silicon Nanowire MOS Field-Effect Transistor

The use of microelectrode array (MEA) to study the protective effects of potassium channel openers on metabolically compromised HL-1 cardiomyocytes

To establish a pharmacological experimental platform for the study of cardiac hypoxia using the microelectrode array

Vertically Stacked Silicon Nanowire Transistors Fabricated by Inductive Plasma Etching and Stress-Limited Oxidation

A unified FinFET reliability model including high K gate stack dynamic threshold voltage, hot carrier injection, and negative bias temperature instability

A web-based platform for nanoscale non-classical device modeling and circuit performance simulation

An analytic model of the silicon-based nanowire Schottky Barrier MOSFET

Characterisation of the Effects of Calcium Channel Blockers and Potassium Channel Openers on HL-1 Cardiomyocytes Using the Microelectrode Array

Computation efficient yet accurate surface potential based analytic model for symmetric DG MOSFETs to predict current-voltage characteristics

Diode Based Gate Oxide Anti-fuse One Time Programmable Memory Array in Standard CMOS Process

Generic compact model development of double-gate MOSFETs with inclusion of different operation modes and channels from heavily doped to intrinsic case

Modeling of hole generation/trapping in ultrathin SiO₂ films during gate injection of electrons in direct tunneling regime

Numerical Simulation of Programming and Read Process for Nano-Scale Phase-Change Memory (PCM) Cell

SET and RESET State Resistance Modeling of Phase Change Memory

A 0.9-V input discontinuous-conduction-mode boost converter with CMOS-control rectifier

A Compact Model of Silicon-Based Nanowire MOSFETs for Circuit Simulation and Design

A Non-Charge-Sheet Analytic Model for Symmetric Double-Gate MOSFETs With Smooth Transition Between Partially and Fully Depleted Operation Modes

A novel source/drain on void (SDOV) MOSFET implemented by local co-implantation of hydrogen and helium

A rigorous carrier-based analytic model for undoped ultra-thin-body silicon-on-insulator (UTB-SOI) MOSFETs

An explicit carrier-based compact model for nanowire surrounding-gate MOSFET simulation

An explicit surface-potential-based model for undoped double-gate MOSFETs

Charge-based model for long-channel cylindrical surrounding-gate MOSFETs from intrinsic channel to heavily doped body

Development of single-transistor-control LDO based on flipped voltage follower for SoC

FinFET reliability study by forward gated-diode generation-recombination current

Full-band quantum transport based simulation for carbon nanotube field effect transistor from chirality to device performance

Generic carrier-based core model for undoped four-terminal double-gate MOSFETs valid for symmetric, asymmetric, and independent-gate-operation modes

Silicon oxynitride integrated waveguide for on-chip optical interconnects applications

The use of microelectrode array (MEA) to study rat peritoneal mast cell activation

Stacked CMOS Technologies

A charge-based compact model for arbitrary doped cylindrical surrounding-gate MOSFETs

A CMOS Active-Pixel Sensor Based DNA Micro-Array with Nano-Metallic Particles Detection Protocol

A Complete Analytic Surface Potential-Based Core Model for Undoped Cylindrical Surrounding-Gate MOSFETs

A complete charge based compact model for silicon nanowire FETs including doping and advanced physical effects

A global continuous channel potential solution for double-gate MOSFETs

A high precision, output-capacitor-free low-dropout regulator for system-on-chip design

A high-power-led driver with power-efficient LED-current sensing circuit

A High-Power-LED Driver with Power-Efficient LED-Current Sensing Circuit

A Surface-Potential-Based Non-Charge-Sheet Core Model for SOI MOSFETs Valid to PD and FD Operation Modes

An auto-selectable-frequency pulse-width modulator for buck converters with improved light-load efficiency

Carrier-Based Approach for Modeling General Four-Terminal Undoped DG-MOSFETs

Circuit Implementation to Describe the Physical Behavior of Phase Change Memory

CMOS-Compatible Zero-Mask One Time Programmable (OTP) Memory Design

Comparison of PN Diodes and FETs as Phase Change Memory (PCM) Driving Devices

Construction of a compact modeling platform and its application to the development of multi-gate MOSFET models for circuit simulation

Construction of a Compact Modeling Platform and Its Application to the Development of Multi-Gate MOSFET Models for Circuit Simulation

Development of multi-gate MOSFET models for circuit simulation with a compact modeling platform

Electrical Stress-Induced Degradation of HfAlO and HfO2 Films of Equal EOT

Electrothermal Coupling and Threshold-switching Simulation Study on Phase Change Memory (PCM) Cell

Generic carrier-based core model for four-terminal double-gate MOSFET valid for symmetric, asymmetric, SOI, and independent gate operation modes

Modeling Nanoscale MOSFETs by a Neural Network Approach

Modeling of PN diode Based Phase-Change Memory Access Circuit

Optimized scaling of diode array design for 32NM node phase change memory

Optimized Scaling of Diode Array Design for 32nm Node Phase Change Memory

Preparation of si nanocrystallites by phase separation of si-rich silicon nitride

Scaling analysis of Phase Change Memory (PCM) driving devices

Surface Potential versus Voltage Equation from Accumulation to Strong Inversion Region for Undoped Symmetric Double-Gate MOSFETs

Universal High Voltage Multiplexer for CMOS OTP Memory Applications

Using the Microelectrode Array (MEA) to Study Hyperpolarising Field Potentials of Non-Excitable Cells

Verilog-A Model for Phase Change Memory Simulation

A carrier-based approach for compact modeling of the long-channel-undoped symmetric double-gate MOSFETs

A CMOS image sensor utilizing opacity of nanometallic particles for DNA detection

A continuous analytic model for undoped (lightly doped) cylindrical surrounding-gate MOSFETs by a carrier-based approach

A high slew-rate push-pull output amplifier for low-quiescent current low-dropout regulators with transient-response improvement

A unified carrier-based model for undoped symmetric double-gate and surrounding-gate MOSFETs

An explicit current-voltage model for undoped double-gate MOSFETs based on accurate yet analytic approximation to the carrier concentration

Analysis of geometry-dependent parasitics in multifin double-gate FinFETs

BSIM5: An advanced charge-based MOSFET model for nanoscale VLSI circuit simulation

Charge carrier generation/trapping mechanisms in HfO2/SiO2 stack

Drug profiling using planar microelectrode arrays

Linear Cofactor Difference Extrema of MOSFET's Drain–Current and Application to Parameter Extraction

On the electrical stress-induced oxide-trapped charges in thin HfO₂/SiO₂ gate dielectric stack

Quasi-SOI MOSFETs - A promising bulk device candidate for extremely scaled era

Temperature-compensated CMOS ring oscillator for power-management circuits

3-Dimensional integration for interconnect reduction in for nano-CMOS technologies

A complete surface potential-based core model for the undoped symmetric double-gate MOSFETs

A new approach to fabricate vertically stacked single-crystalline silicon nanowires

A Unified Carrier-Based Model for Symmetric Double-Gate and Surrounding-Gate MOS Transistors

ALTRAS-CNFET: Full-band based quantum transport simulator for carbon nanotube field effect transistor engineering: From chirality to device performance

An approximate carrier-based compact model for fully depleted surrounding-gate MOSFETs with finite doping body

An Explicit Carrier-Based Compact Model for Surrounding-Gate MOSFETs

Analysis of switching-loss-reduction methods for MHz-switching buck converters

Capturing cellular communication with guided electrode network on a silicon integrated circuit chip

Compact Modeling of Nano-Scale Surrounding-Gate MOSFETs: Potential-Based Model and Discussion on Complex Sub-threshold Characteristics

Complicated subthreshold Behavior of undoped cylindrical surrounding-gate MOSFETs

Design of area-efficient, low-quiescent-current LDOs for chip-level power management

Design of Area-Efficient, Low-Quiescent-Current LDOs for Chip-Level Power Management

Design of fast-response on-chip current sensor for current-mode controlled buck converters with MHz switching frequency

Effect of technology scaling on temperature independent point (TIP) in MOS transistors

From Chirality to Device Performance: Full-Band Based Quantum Transport Simulation for Carbon Nanotube Field Effect Transistor

Generic Carrier-Based Approach to Develop Compact Models of Non-Classical CMOS Devices

Microwave plasma anneal to fabricate silicides and restrain the formation of unstable phases

Modeling of geometry-induced RF characteristics of double-gate MOSFETs

Modeling of Multi-fin MOSFET Parasitic Effects

Modeling the geometry-dependent parasitics in multi-fin FinFETs

OTP memory for low cost passive RFID tags

Photoluminescence of silicon nitride-embedded silicon nanocrystallites prepared by thermal annealing of si-rich silicon nitride

Reduction of interconnect loading in sub-100nm technology by 3D stacked-FinCMOS

Reliability Analysis of Thin HfO2/SiO2 Gate Dielectric Stack

The impact of device structure and quantum mechanics on effective E-field in ultra-thin body and double-gate SOI MOSFETs

A carrier-based analytic DCIV model for long channel undoped cylindrical surrounding-gate MOSFETs

A continuous analytic I-V model for long-channel undoped ultra-thin-body silicon-on-insulator (UTB-SOI) MOSFETs from a carrier-based approach

A new analytic method to design multiple floating field limiting rings of power devices

A physics-based analytic solution to the MOSFET surface potential from accumulation to strong-inversion region

A wide-band T/R switch using enhanced compact waffle MOSFETs

An analytic model to account for quantum-mechanical effects of MOSFETs using a parabolic potential well approximation

BSIM model research and recent progress

BSIM Model Research and Recent Progress

Current transport and high-field reliability of aluminum/hafnium oxide/silicon structure

Direct tunneling stress-induced leakage current in ultrathin HfO2/SiO2 gate dielectric stacks

Electrical characteristics of high-κ dielectric film grown by direct sputtering method

Enhancing deoxyribonucleic acid (DNA) detection sensitivity through microconcentration on patterned fluorocarbon polymer surface

Experimental evidence of two conduction mechanisms for direct tunnelling stress-induced leakage current through ultrathin silicon dioxide gate dielectrics

Gate resistance modeling of multifin MOS devices

Local clustering 3-D stacked CMOS technology for interconnect loading reduction

Minimizing hydrogen content in silicon oxynitride by thermal oxidation of silicon-rich silicon nitride

Silicon oxynitride prepared by chemical vapor deposition as optical waveguide materials

Silicon-on-nothing MOSFETs fabricated with hydrogen and helium co-implantation

Stressing effects on the charge trapping of silicon oxynitride prepared by thermal oxidation of LPCVD Si-rich silicon nitride

3-dimensional integration for interconnect reduction in for nano-CMOS technologies

A carrier-based analytic model for undoped (lightly doped) ultra-thin-body silicon-on-insulator (UTB-SOI) MOSFETs

A carrier-based analytic model for undoped surrounding-gate MOSFETs

A CMOS-control rectifier for discontinuous-conduction mode switching DC-DC converters

A complete carrier-based non-charge-sheet analytic theory for nano-scale undoped surrounding-gate MOSFETs

A Single Chip Micro-DNA-Array System Based on CMOS Image Sensor Technology

A zero-mask one-time programmable memory array for RFID applications

Benchmark tests on conventional surface potential based charge-sheet models and the advanced PUNSIM development

Carrier-Based Approach: A Generous Strategy to Develop Compact Model of Non-Classical CMOS

Fabrication of optical waveguide using silicon oxynitride prepared by thermal oxidation of silicon rich silicon nitride

PECVD growth of thick silicon oxynitride for on-chip optical interconnects applications

PUNSIM: An advanced surface potential based MOSFET model

A 2-bit highly scalable nonvolatile memory cell with two electrically isolated charge trapping sites

A CMOS Active Pixel Sensor Based DNA Micro-Array with Nano-Metallic Particles Detection Protocol

A CMOS-compatible DNA, microarray using optical detection together with a highly sensitive nanometallic particle protocol

A compact model to predict quantized sub-band energy levels and inversion layer centroids of MOSFETs with a parabolic potential well approximation

A DNA-detection platform with integrated photodiodes on a silicon chip

A highly scalable opposite side floating-gate flash memory cell

A three-dimensional stacked Fin-CMOS technology for high-density ULSI circuits

An air spacer technology for improving short-channel immunity of MOSFETs with raised source/drain and high-k gate dielectric

An integrated CMOS current-sensing circuit for low-voltage current-mode buck regulator

Backside-illuminated lateral PIN photodiode for CMOS image sensor on SOS substrate

Charge-based core and the model architecture of BSIM5

Compact modeling of transient substrate current of MOSFET

Effects of dopants on the electrical behavior of grain boundary in metal-induced crystallized polysilicon film

Effects of layout methods of RF CMOS on noise performance

Impacts of nonrectangular fin cross section on the electrical characteristics of FinFET

Optimization of base-to-emitter spacer thickness to maximize the frequency response of bipolar transistors

A capped trimming hard-mask patterning technique for integration of nano-devices and conventional integrated circuits

A CMOS-compatible WORM memory for low-cost non-volatile memory applications

A Physical Short-Channel Threshold Voltage Model for FinFET's with Non-rectangular Cross-section

Compact modeling of FinFETs featuring independent-gate operation mode

Complete Carrier-Based Non-Charge-Sheet Analytic Model for Nano-Scale Undoped Symmetric Double-Gate MOSFETs, Hong Kong

Direct tunneling stress-induced leakage current in NMOS devices with ultrathin gate oxides

Layout effects on design optimization of CMOS LNA and mixer

Multi-electrode arrays (MEAs) with guided network for cell-to-cell communication transduction

Novel localized-SOI MOSFET's combining the advantages of SOI and bulk substrates for highly-scaled devices

Parasitic minimization in RF multi-fin FETs

A self-aligned gate-all-around MOS transistor on single-grain silicon

A stacked CMOS technology on SOI substrate

A statistical model to predict the performance variation of polysilicon TFTs formed by grain-enhancement technology

A workable use of the floating-body silicon-on-sapphire MOSFET as a transconductance mixer

Analysis and optimization of SDOI structure to maximize the intrinsic performance of extremely scaled MOSFETs

Characterization of double gate MOSFETs fabricated by a simple method on a recrystallized silicon film

Effects of gate material on Fowler-Nordheim stress induced thin silicon dioxide degradation under negative gate bias

Effects of spacer thickness on noise performance of bipolar transistors

Large-grain polysilicon crystallization enhancement using pulsed RTA

Modeling of large-grain polysilicon formation under retardation effect of SPC

Modeling the floating-body effects of fully depleted, partially depleted, and body-grounded SOI MOSFETs

Self-align recessed source drain ultrathin body SOI MOSFET

SOI flash memory scaling limit and design consideration based on 2-D analytical modeling

The impact of the distributed RC effect on high frequency noise modeling of bipolar transistor

A highly manufacturable nano-metallic particle based DNA micro-array

A non-charge-sheet analytic theory for undoped symmetric double-gate MOSFETs from the exact solution of Poisson's equation using SPP approach

A non-charge-sheet based analytical model of undoped symmetric double-gate MOSFETs using SPP approach

A Physics Based Analytical Model of Undoped Body MOSFETs

A Physics Based Analytical Solution to Undoped Cylindrical Surrounding-Gate (SRG) MOSFETs

A Study of Source/Drain-On-Insulator Structure for Extremely Scaled MOSFETs

A Waffle Layout Design Method for High Frequency MOSFETs

An exact analytic model of undoped body MOSFETs using the SPP approach

BSIM5 MOSFET Model

Characterization and modeling of waffle MOSFETs for high frequency applications

DNA detection by self-assembled nano-particle and integrated photodiodes

DNA Detection by Self-Assembled Nano-Particle and Integrated Photodiodes

High frequency characteristics of MOSFETs with compact waffle layout

Impact of transistor-to-grain size statistics on large-grain polysilicon TFT characteristics

Integrated circuit based biosensor technologies for DNA-microarray applications

Linear cofactor difference extrema of MOSFET's drain current and their application in parameter extraction

Modeling CMOS Non-Quasi-Static Effects in a Quasi-Static Simulation Engine

Multi-bit MONOS nonvolatile memory based on double-gate technology

Optimizations of Spacer Thickness for Minimizing Noise Performance of Bipolar Transistors

Quasi-2D compact modeling for double-gate MOSFET

Self-aligned recessed source/drain ultra-thin body SOI MOSFET technology

Statistical modeling of grain-enhanced polysilicon thin-film transistor in consideration of grain boundary distribution

Surface-potential-plus approach for next generation CMOS device modeling

The development of the next generation BSIM for sub-100nm mixed-signal circuit simulation

The next generation BSIM for sub-100nm mixed-signal circuit simulation

The Next Generation BSIM Model Extending from Conventional to Double-Gate MOSFETs

Three dimensional analytical subthreshold model for non-rectangular cross-section FinFETs

Three-dimensional Stacked-Fin-CMOS integrated circuit using double layer SOI material

0.5 mu m silicon-on-sapphire metal oxide semiconductor field effect transistor for RF power amplifier applications

A 1-v 3.5-mw CMOS switched-opamp quadrature IF circuitry for Bluetooth receivers

A 2-bit MONOS nonvolatile memory cell based on asymmetric double gate MOSFET structure

A compact SOI MOS transistor model for distortion analysis

A High-Densigy Conduction-Based Micro-DNA Identification Array Fabricated With a CMOS Compatible Process

A self-aligned, electrically separable double-gate MOS transistor technology for dynamic threshold voltage application

A SPICE model for thin-film transistors fabricated on grain-enhanced polysilicon film

A viable self-aligned bottom-gate MOS transistor technology for deep submicron 3-D SRAM

Amplifying the electrical hybridization signals of DNA array by multilayer assembly of Au nanoparticle probes

An elevated source/drain-on-insulator structure to maximize the intrinsic performance of extremely scaled MOSFETs

An enhanced compact waffle MOSFET with low drain capacitance from a standard submicron CMOS technology

Area-efficient CMOS charge pumps for LCD drivers

Effects of floating body on double polysilicon partially depleted SOI nonvolatile memory cell

High-isolation bonding pad design for silicon RFIC up to 20 GHz

Modeling of grain growth mechanism by nickel silicide reactive grain boundary effect in metal-induced-lateral-crystallization

On the-body-source built-in potential lowering of SOI MOSFETs

Practical compact modeling approaches and options for sub-0.1 mu m CMOS technologies

RF characterization of metal T-Gate structure in fully-depleted SOICMOS technology

2D analysis of bottom gate misalignment and process tolerant for sub-100nm symmetric double-gate MOSFETs

A CMOS Active Pixel Sensor on Silicon-on-Sapphire Substrate with Backside Illumination

A framework for generic physics based double-gate MOSFET modeling

A high density conduction based micro-DNA-identification array fabricated in a CMOS compatible process

A highly scalable 2-bit asymmetric double-gate MOSFET nonvolatile memory

A new digital-pixel architecture for CMOS image sensor with pixel-level ADC and pulse width modulation using a 0.18 mu m CMOS technology

A physics-based analytical surface potential and capacitance model of MOSFET's operation from accumulation to depletion region

A unified model for partial-depletion and full-depletion SOI circuit designs: Using BSIMPD as a foundation

A Workable Use of Floating-Body SOS MOSFET as a Transconductance Mixer

An active pixel sensor (APS) based on high gain CMOS compatible lateral bipolar transistor (LBT) on SOS substrate with backside illumination

An Active Pixel Sensor (APS) Based on High Gain CMOS Compatible Lateral Bipolar Transistors (LBT) on SOS Substrate with Backside Illumination

An advanced surface-potential-plus MOSFET model

An highly scalable double density nonvolatile memory cell using two electrically isolated oxide-nitride-oxide charge storage stacks

Circuit Performance of Double-Gate SOI CMOS

Compact modeling for RF and microwave integrated circuits

Comparative analysis and parameter extraction of enhanced waffle MOSFET

Design of sub 50nm ultrathin-body (UTB) SOI MOSFETs with raised S/D

Design of Sub-50nm Ultrathin-Body (UTB) SOI MOSFETs with Raised S/D

Direct Electrical Characterization of Metal Induced Lateral Crystallization Regions by Spreading Resistance Probe Measurements

Impact of Non-Vertical Sidewall on Sub-50 nm FinFET

Large-signal and Phase Noise Performance Analysis of Active Inductor Tunable Oscillators

Miniaturized 3D endoscopic imaging system

Modeling of direct tunneling current in multi-layer gate stacks

Multi-electrode Arrays (MEAs) with guided network for cell-to-cell communication transduction

The Impact of Scaling on Volume Inversion in Symmetric Double-Gate MOSFETs

The impact of the AC current crowding effect on BJT RF noise modeling

A 1.0-V V-DD CMOS active-pixel sensor with complementary pixel architecture and pulsewidth modulation fabricated with a 0.25-mu m CMOS process

A low-voltage CMOS complementary active pixel sensor (CAPS) fabricated using a 0.25 mu m CMOS technology

A simple method for optimization of 6H-SiC punch-through junctions used in both unipolar and bipolar power devices

Design methodology of the high performance large-grain polysilicon MOSFET

Determining the onset frequency of nonquasistatic effects of the MOSFET in AC simulation

Equivalent junction method to predict 3-D effect of curved-abrupt p-n junctions

High Quality HfO 2 Film and Its Applications in Novel Poly-Si Devices

Implementation and characterization of self-aligned double-gate TFT with thin channel and thick source/drain

Implementation of fully self-aligned bottom-gate MOS transistor

Linearly graded doping drift region: A novel lateral voltage-sustaining layer used for improvement of RESURF LDMOS transistor performances

Normalized mutual integral difference method to extract threshold voltage of MOSFETs

Normalized mutual integral difference operator: A novel experimental method for extracting threshold voltage of MOSFETs

Reduction of off-current in self-aligned double-gate TFT with mask-free symmetric LDD

SOI数模混合集成电路的串扰特性分析

Study of grain growth of polysilicon formed by nickel-induced-lateral-crystallization of amorphous silicon and subsequent high temperature annealing

适用于数模混合集成的SOI MOSFET的失真分析

A 0.9-V 0.2-mu w CMOS single-opamp-based switched-opamp Sigma Delta modulator for pacemaker applications

A 1.0 V V_DD CMOS active pixel image sensor with complementary pixel architecture fabricated with a 0.25 μm CMOS process

A 1.0 V V_DD CMOS active pixel image sensor with complementary pixel architecture fabricated with a 0.25 μm CMOS process

A Comparative Study of RF Noise Characteristics of Different Submicron SOI MOSFET Structures on SIMOX Technology

A highly integrated CMOS image sensor architecture for low voltage applications with deep submicron process

A New Correlated Double Sampling (CDS) Technique for Low Voltage Design Environment in Advanced CMOS Technology

A self-aligned double-gate MOS transistor technology with individually addressable gates

A self-assembly conductive device for direct DNA identification in integrated microarray based system

A Viable Self-aligned Bottom-Gate MOSFET Technology for High Density and Low Voltage SRAM

Amorphous silicon deposition temperature optimization on advanced polysilicon thin-film formation using metal-induced lateral crystallization technology

An Enhanced Compact Waffle MOSFET for RF Integrated Circuits

An impact ionization model for SOI circuit simulation

An opposite side floating gate flash memory scalable to 20 nm length

Approaches and options for modeling sub-0.1 μm CMOS devices

Area efficient CMOS integrated charge pumps

Array-Based Electrical Detector of Integrated DNA Identification System for Genetic Chip Applications

Characteristics of high quality hafnium oxide gate dielectric

Electrical characteristics of novel hafnium oxide film

Evaluation of the partially-depleted silicon-on-sapphire technology for microwave amplifiers and other prospective applications

Grain quality enhancement of nickel-crystallized polysilicon film in quantum-wire-like structures

High precision physical model for nickel MILC

High quality HfO₂ film and its applications in novel poly-si devices

High-isolation bonding pad with depletion-insulation structure for RF/microwave integrated circuits on bulk silicon CMOS

High-Speed Mixed Signal and RF Circuits Design with Compact Waffle MOSFET

Improved SOI image sensor design based on backside illumination on silicon-on-sapphire (SOS) substrate

Modeling of metal-induced-lateral-crystallization mechanism for optimization of high performance thin-film-transistor fabrication

Modeling of Metal-Induced-Lateral-Crystallization Mechanism in High Performance Low Temperature Thin-Film-Transistor Application

New MEMS technology using multi-layer NILC poly-Si and NiSi films

On mechanism of nickel diffusion during metal induced lateral crystallization of amorphous silicon

RF Power Characteristics of Thin Film Silicon-on-Sapphire MOSFET

Surface Characterization of DNA Microarray on Silicon Dioxide and Compatible Silicon Materials in the Immobilization Process

Symmetry realization of BSIM model with dynamic reference method for circuit simulation

Tendency for full depletion due to gate tunneling current

The engineering of BSIM for the nano-technology era and beyond

The gate misalignment effects of the sub-threshold characteristics of sub-100 nm DG-MOSFETs

Transient Behavior of Partially Depleted SOI Non-Volatile Memory Cell and Its Impacts on Device Scaling

A High Gain n-well/gate Tied PMOSFET Image Sensor Fabricated from a Standard CMOS Process

A low voltage hybrid bulk/SOI CMOS active pixel image sensor

A novel self-aligned bottom gate poly-Si TFT with in-situ LDD

A novel self-aligned double-gate TFT technology

A SMIL browser with an enhanced image, audio and video effect library for multimedia rich presentations

Characterization of MOSFETs fabricated on large-grain polysilicon on insulator

Design of Wide MOSFETs on Re-Crystallized Polysilicon Film with Multigigahertz Cut-Off Frequency

Development of a Viable 3D Integrated Circuit Technology

Effects of longitudinal and latitudinal grain boundaries on the performance of large-grain polysilicon MOSFET

High frequency performance of large-grain polysilicon-on-insulator MOSFETs

High quality thermal oxide on LPSOI formed by high temperature enhanced MILC

MOSFET drain/source charge partition under nonquasi-static switching

Multiple layers of CMOS integrated circuits using recrystallized silicon film

Three-dimensional CMOS SOI integrated circuit using high-temperature metal-induced lateral crystallization

3D integrated circuit using large grain polysilicon film

A Closed-Form Thermal Noise Model of SOI MOSFETs for Low Noise Application

A new active pixel sensor (APS) architecture on SOI substrate for low voltage operation

A novel sub-50 nm poly-Si gate patterning technology

A Self-aligned Bottom Gate Poly-Si TFT Technology

A self-aligned double-gate polysilicon TFT technology

A Simple Method to Fabricate Double-Gate SOI MOSFET with Diffusion Layer on Bulk Silicon Wafer as the Bottom Gate

A Study of the Spectral Sensitivity of Photodiode From a Standard CMOS Process for DNA Detection

A Unified Predictive TFT Model with Capability for Statistical Simulation

Analysis of aligned polysilicon grain boundaries effects on the performance of large-grain polysilicon MOSFET

Characteristics of RF power amplifiers by 0.5μm SOS CMOS process

Characterization of Immobilized DNA Probes on the Surface of Silicon Compatible Materials

Distortion simulation of 90nm nMOSFET for RF Applications

Double-gate SOI MOSFET Fabrication from Bulk Silicon Wafer

Effects of process conditions on the performance of large grain poly-silicon on insulator (LPSOI) MOSFET for advanced CMOS applications

Evaluation of the Impact of Non-Quasi-Static Effects in RF Applications

Fabrication and Properties of Self-aligned Double-Gate Poly-Si TFT

Improved oxide quality on polysilicon by enhanced Metal-Induced-Lateral-Crystallization (MILC)

Integrated DNA Detection System on Silicon Substrate With Photodiodes

Integrated Photodiode DNA Identification System for Genetic Chip Applications

Low voltage CMOS active pixel sensor design methodology with device scaling considerations

New MENS Technology Using Multi-Layer NILC Poly-Si And NiSi Films

Optical Response of Photodiode in Integrated DNA Detection System

Realization of compact MOSFET structure by waffle-layout

Switched-capacitor power converters with integrated low dropout regulators

The approach to rail-to-rail CMOS active pixel sensor for portable applications

The potential and realization of multi-layers three-dimensional integrated circuit

The silicon-on-sapphire technology for RF integrated circuits: Potential and limitations

CMOS devices - Device scaling

Effect of electric field on metal induced lateral crystallization of amorphous silicon

High gain gate/body tied NMOSFET photo-detector on SOI substrate for low power applications

LETTERS-Silicon Alloys and Thin Film-Submicron Super TFTs for 3-D VLSI Applications

Performance of the floating gate/body tied NMOSFET photodetector on SOI substrate

Resistivity and thermal stability of nickel mono-silicide

Submicron super TFTs for 3-D VLSI applications

Super thin-film transistor with SOI CMOS performance formed by a novel grain enhancement method

The behavior of narrow-width SOI MOSFET's with MESA isolation

Effect of nickel in large grain poly-Si film formed by nickel induced lateral crystallization and new grain enhancement method

Effect of ramp annealing to Ni induced lateral crystallization of amorphous silicon

Effects of grain boundaries on TFTs formed by high-temperature MILC

Large-grain polysilicon MOSFET for 3-D integrated circuits

Opposite side floating gate SOI FLASH memory cell

Performance of Submicron Large-Grain Polysilicon-on-Insulator (LPSOI) MOSFETs Formed by Crystallization of Amorphous Silicon

SOI Formation from Amorphous Silicon by Novel Grain Enhancement Method

TFT fabrication on MILC polysilicon film with pulsed rapid thermal annealing

Three dimensional CMOS integrated circuits on large grain polysilicon films

Fully depleted CMOS/SOI device design guidelines for low-power applications

An enhanced BSIM3 NQS model for large signal transient simulation

Building hybrid active pixels for CMOS imager on SOI substrate

Improved thin dielectric characteristics on chemical-mechanically polished polycrystalline silicon film

Improved thin-film transistor (TFT) characteristics on chemical-mechanically polished polycrystalline silicon film

Physical approach to enhance BSIM3 NQS model for fast transient simulation

Process windows of titanium, cobalt and nickel silicide in deep submicron polysilanes

Single grain thin-film-transistor (TFT) with SOI CMOS performance formed by metal-induced-lateral-crystallization

SOI formation from amorphous silicon by metal-induced-lateral-crystallization (MILC) and subsequent high temperature annealing

A Robust and Physical BSIM3 Non-quasi-static Transient and AC Small-signal Model for Circuit Simulation

A unified understanding on fully depleted SOI NMOSFET hot-carrier degradation

Impact of scaling silicon film thickness and channel width on SOI MOSFET with reoxidized MESA isolation

Investigation of recessed channel SOI devices

On the power dissipation in dynamic threshold silicon-on-insulator CMOS inverter

Performance of a CMOS compatible lateral bipolar photodetector on SOI substrate

SESSION 4: SILICON AND SILICON COMPOUND DEVICES

Stability of NiSi in boron-doped polysilicon lines

VLSI process integration

A new approach to study the channel charge partition of MOS transistors during non-quasi-static (NQS) turn-on

Dynamic depletion SOI MOSFET model for SPICE

High responsivity photo-sensor using gate-body tied SOI MOSFET

High-Q SOI gated varactor for use in RF ICs

Novel high-gain CMOS image sensor using floating N-well/gate tied PMOSFET

Process windows of nickel silicide films

Process windows of titanium, cobalt and nickel silicide in deep submicron poly-Si lines

Properties and design optimization of photo-diodes available in a current CMOS technology

The Investigateion of Recessed Channel SOI Devices

Thermal stability of nickel silicides in different silicon substrates

A physical and scalable I-V model in BSIM3v3 for analog/digital circuit simulation

AC output conductance of SOI MOSFET's and impact on analog applications

Inverse-narrow-width effect of deep sub-micrometer MOSFETs with LOCOS isolation

Analysis of Floating Body Effect in Non-fully Depleted SOI MOSFETs based on Capacitive Coupling

Fully depleted CMOS/SOI device design guidelines for low power applications

On the Power Dissipation in Dynamic Threshold Silicon-on-insulator CMOS inverter

Photon induced hump effect in NMOSFET

Plasma Immersion Ion Implantation (PIII) and SOI synthesis

Reoxidized MESA isolated SOI MOSFET width scaling as a function of silicon film thickness

Thermal stability of nickel silicide films in submicron p-type polysilicon lines

A Physically IBased Compact Device Model for Fully Depleted and. Nearly Fully Depleted SO1 MOSFET

A Study of Deep-submicron MOSFET Technology Prediction and Scaling with BSIM3

Experimental characterization of transient floating body effect in non-fully depleted SOI MOSFET

Frequency dispersion in partially depleted SOI MOSFET output resistance

Impact of scaling silicon film thickness on hot carrier effects in thin film fully depleted SOI MOSFETs

Investigation on the robustness, accuracy and simulation performance of a physics-based deep-submicrometer BSIM model for analog/digital circuit simulation

Multicode high-speed transmission with interference cancellation for wireless personal communications

COMPARATIVE-STUDY OF FULLY DEPLETED AND BODY-GROUNDED NON-FULLY DEPLETED SOI MOSFETS FOR HIGH-PERFORMANCE ANALOG AND MIXED-SIGNAL CIRCUITS

ESD RELIABILITY AND PROTECTION SCHEMES IN SOI CMOS OUTPUT BUFFERS

Polysilicon gate depletion effect on IC performance

SOI/bulk hybrid technology on SIMOX wafers for high performance circuits with good ESD immunity

A Unified BSIM I-V Model for Circuit Simulation

Anomalous narrow width behavior of deep sub-micrometer MOSFET's with LOCOS isolation

High performance lateral bipolar transistor from a SOI CMOS process

Narrow width effect of ROSIE isolated SOI MOSFET

Novel SOI CBiCMOS compatible device structure for analog and mixed-mode circuits

Physically based device model for fully depleted and nearly fully depleted SOI MOSFET

SOI MOSFET design for all-dimensional scaling with short channel, narrow width and ultra-thin films

Hot-carrier effects in thin-film fully depleted SOI MOSFET's

Recessed-channel structure for fabricating ultrathin SOI MOSFET with low series resistance

Body Self Bias in Fully Depleted and Non-Fully Depleted SOI Devices

Characterization of hot-carrier effects in thin-film fully-depleted SOI MOSFETs

Comparison of ESD protection capability of SOI and BULK CMOS output buffers

High Performance Bulk MOSFET Fabricated on SOI Substrate for ESD Protection and Circuit Applications

Interface Characterization of Fully-Depleted SOI MOSFET by a Subthreshold I-V Method

Relaxation time approach to model the non-quasi-static transient effects in MOSFET's

A Low-Barrier Body-Contact Scheme for SOI MOSFETs to Eliminate the Floating Body Effect

Recess channel structure for reducing source/drain series resistance in ultra-thin SOI MOSFET

Experimental Investigation of Recessed Channel SOI Devices

Circular Electrodes to Reduce the Current Variation of OTFTS With the Drop-casted Semiconducting Layer

Article

Contact Resistance Reduction of Carbon Nanotube via through O₂ Plasma Post-Synthesis Treatment

Article

High-resolution flexible AMOLED display integrating gate driver by metal-oxide TFTs

Article

On the Formulation of Self-Heating Models for Circuit Simulation

Article

On-Demand Band-Rejected Wideband Antenna Based on Peelable Resonator Membrane

Article

Origin of Nonideal Graphene-Silicon Schottky Junction

Article

Prototyping of Terahertz Metasurface by One-Step Lithographically Defined Templating

Article

Self-Driven Metal–Semiconductor–Metal WSe2 Photodetector with Asymmetric Contact Geometries

Article

同质结隧穿场效应晶体管 and 异质结隧穿场效应晶体管

Book chapter

A Smooth and Continuous Phase Change Memory SPICE Model for Improved Convergence

Conference paper

An effective mobility model for tunneling double-gate MOSFET (T-FinFET)

Conference paper

Band-rejected Wideband Antenna Based on Peelable Resonator Membrane

Conference paper

Carbon Enhanced BEOL Technology

Conference paper

Carrier Injection Mechanism of Metal-MoS₂ Ohmic Contact in MoS₂ FETs

Conference paper

CMOS Technology with Integrated Carbon-Nanotube Contact Plugs

Conference paper

Compact Models for Giga-Scale Memory System

Conference paper

Current Conduction Mechanisms in h-BN as a Dielectric Material

Conference paper

Current Enhancement of Graphene-Inserted Tunneling Contact IGZO TFT

Conference paper

Engineering of Graphene-to-Semiconductor Contacts

Conference paper

i-MOS: a Cloud-based Circuit Simulation and Compact Modeling Platform

Conference paper

Impact of CNT Diameter Distribution on CNT filled Via Scaling

Conference paper

Synthesis of Carbon Nanotube in Sub-100nm Vias on Ni Silicide

Conference paper

Ultra-Low-k Interlayer Dielectric for Post-Moore CMOS Interconnect

Conference paper

A 1.2V-to-0.4V 3.2GHz-to-14.3MHz Power-Efficient 3-Port Register File in 65-nm CMOS

Article

A 140mV Variation-Tolerant Deep Sub-Threshold SRAM in 65nm CMOS

Article

A Low-Power Ring Oscillator Using Pull-Up Control Scheme Integrated by Metal-Oxide TFTs

Article

Artificial Neural Network Design for Compact Modeling of Generic Transistors

Article

Doping of Two-dimensional MoS₂ by High Energy Ion Implantation

Article

Exchange bias study of sub-100 nm-diameter CoFeB/IrMn antidot and nanodot arrays fabricated by nanosphere lithography

Article

High-Current Drivability Fibonacci Charge Pump With Connect-Point-Shift Enhancement

Article

Low Frequency Behavior of CVD Graphene from DC to 40 GHz

Article

Low Power Phase Change Memory With Vertical Carbon Nanotube Electrode

Article

Numerical Study on Random Dopant Fluctuation Effects on T-FinFET Performance

Article

Reduced Magnetic Coercivity and Switching Field in NiFeCuMo/Ru/NiFeCuMo Synthetic-ferrimagnetic Nanodots

Article

Synthesis and Interface Characterization of CNTs on Graphene

Article

Tunneling Contact IGZO TFTs with Reduced Saturation Voltages

Article

Silicon-Based Junctionless MOSFETs: Device Physics, Performance Boosters and Variations

Book chapter

A Design Methodology of Efficient On-Chip Wireless Power Transmission

Conference paper

A Universal Approach for Signal Dependent Circuit Reliability Simulation

Conference paper

A Voltage-Scalable Zero-Delay-Overhead Scheme for Standby Power Reduction in Dynamic Register Files

Conference paper

BEOL Technology for Heterogeneous System Integration

Conference paper

Catalyst Design for High-Density and Low-Temperature CNT Synthesis on Conductive Ti Silicide Substrate

Conference paper

Concurrent Device/circuit Aging for General Reliability Simulations

Conference paper

Design Considerations for Mechanically Stable Air-Gap Interconnect

Conference paper

Gate-Controlled Electron Injection in Tunneling Contact IGZO TFTs

Conference paper

Modeling of Fringe Current for Semiconductor-Extended Organic TFTs

Conference paper

Ohmic Contact Formation Between Ge₂Sb₂Te₅ Phase Change Material and Vertically Aligned Carbon Nanotubes

Conference paper

Temperature Compensated Super-High-Frequency (2-8 GHz) Surface Acoustic Wave Devices

Conference paper

A 200-Channel Area-Power-Efficient Chemical and Electrical Dual-Mode Acquisition IC for the Study of Neurodegenerative Diseases

Article

A Compact Low-Power 4-Port Register File with Grounded Write Bitlines and Single-Ended Read Operations

Article

A Compact Model for Double-Gate Heterojunction Tunnel FETs

Article

A High Conversion Ratio Component-Efficient Charge Pump for Display Drivers

Article

A High-Voltage (> 600 V) N-Island LDMOS With Step-Doped Drift Region in Partial SOI Technology

Article

A physics based analytic model for gate all around MOSFETs with SiO₂-Core Si-shell architecture

Article

A Short Channel Double-gate Junctionless Transistor Model Including the Dynamic Channel Boundary Effect

Article

Analytical Current Model for Long-Channel Junctionless Double-Gate MOSFETs

Article

Carbon Nanotube Contact Plug on Silicide for CMOS Compatible Interconnect

Article

Carrier Type Control of WSe₂ Field-Effect Transistors by Thickness Modulation and MoO₃ Layer Doping

Article

Depth-of-Focus Determination for Talbot Lithography of Large-Scale Free-Standing Periodic Features

Article

Doping Enhanced Barrier Lowering in Graphene-Silicon Junctions

Article

Effect of Near-Field Diffraction in Photolithography of Hexagonal Arrays for Dichroic Filters

Article

Field-Angle and DC-Bias Dependence of Spin-Torque Diode in Giant Magnetoresistive Microstripe

Article

Metal-Oxide-Semiconductor Field-Effect Transistor Resonant Detection on Terahertz Radiation in Optical Exciting Regime

Article

Modeling CNTFET Performance Variation due to Spatial Distribution of Carbon Nanotubes

Article

Ultralow-k Dielectric With Nanotubes Assisted Vertically Aligned Cylindrical Pores

Article

Universal framework for temperature dependence prediction of the negative bias temperature instability based on microscope pictures

Article

Tunneling Field Effect Transistor Technology

Book

Compact Models of TFETs

Book chapter

Steep Slope Devices and TFETs

Book chapter

A Sustainable Strategy of Farming in Radioactive Contaminated Farmland: A Case Study in Fukushima

Conference paper

Applications of Carbon-Nanotubes in CMOS Interconnect Technology Enhancement

Conference paper

Breakdown Mechanism of Horizontally Aligned Carbon Nanotube (CNT)

Conference paper

Carbon Nanotube Assisted Interconnect Technology

Conference paper

Carbon Nanotube Enhanced CMOS Interconnect

Conference paper

Dynamic NBTI Simulation Coupling with Self-Heating Effect in SOI MOSFETs

Conference paper

Exchange Bias Study of CoFeB/IrMn Antidot and Nanodot Arrays Fabricated by Nanosphere Lithography

Conference paper

Fabrication and Measurement of Millimeter-Wave On-chip MIMO Antenna for CMOS RFIC's

Conference paper

Fully Transparent Solution-Processed Carbon Nanotube Thin Film Transistors On a Flexible Substrate

Conference paper

Modeling Current Reduction for PCM Cell with Thermal Buffer Layer

Conference paper

Modeling of Planar Spreading of Current for OTFT of Low Aspect Ratio

Conference paper

Modeling spatial distribution induced variability in CNT array based FETs

Conference paper

Patterning CNT-forest for the Fabrication of Nano-Channel OFET of High W/L

Conference paper

Reduced Magnetic Coercivity and Switching Field in Conetic-Alloy-Based Synthetic-Ferrimagnetic Nanodots

Conference paper

Reliability-aware Device Compact Modeling and Implications On Circuit Aging Simulations

Conference paper

Study Progress on FET-based Terahertz Wave Generation and Detection

Conference paper

Characterization of interface trap dynamics responsible for hysteresis in organic thin-film transistors

Article

Comparative Analysis of Carrier Statistics on MOSFET and Tunneling FET Characteristics

Article

Eight-FinFET Fully Differential SRAM Cell With Enhanced Read and Write Voltage Margins

Article

Extraction and modeling of layout-dependent MOSFET gate-to-source/drain fringing capacitance in 40 nm technology

Article

Flexible structured high-frequency film bulk acoustic resonator for flexible wireless electronics

Article

Gate Capacitance Model for Aligned Carbon Nanotube FETs With Arbitrary CNT Spacing

Article

Low voltage and high ON/OFF ratio field-effect transistors based on CVD MoS2 and ultra high-k gate dielectric PZT

Article

Resistance Determination for Sub-100-nm Carbon Nanotube Vias

Article

Self-aligned offset gate poly-Si TFTs using photoresist trimming technology

Article

SRAM precharge system for reducing write power

Article

Suppression of subthreshold characteristics variation for junctionless multigate transistors using high-k spacers

Article

Analytic High Frequency Model of SOI-MOSFETs with Active Transmission Line Analysis

Book chapter

A 50-Ohm Semi-enclosed Stripline Design in a 90nm CMOS Process for 60-GHz Millimeter- Wave Integrated Circuits

Conference paper

A 65nm 3.2GHz 44.2mW Low-Vt Register File with Robust Low-capacitance Dynamic Local Bitlines

Conference paper

All-Carbon Interconnect: Fabrication and Integration

Conference paper

An Area-Efficient 1.5-GHz Dual-V_DD 4-Port Register File for Real-Time Microprocessors

Conference paper

Compact Transmission Line Design in a Multi-Metallization Nano-CMOS Process for Millimeter-Wave Integrated Circuits

Conference paper

Efficient On-Chip Wireless Power Transmission

Conference paper

Efficient wireless power transmission technology based on above-CMOS integrated (ACI) high quality inductors

Conference paper

Improved Electrical Stability of Double-gate a-IGZO TFTs

Conference paper

Interface Engineering to Enhance Phase Change Memory Programmability

Conference paper

Investigation of Nitrogen Enhanced NBTI Effect Using the Universal Prediction Model

Conference paper

Modeling active dimension for phase change memory cell

Conference paper

Modeling of On-Chip Wireless Power Transmission System

Conference paper

Nanoscale Register File Circuit Design – Challenges and Opportunities

Conference paper

Write Ability Enhancement Techniques for L1 Cache on Next-Generation IBM POWER^TM Processors

Conference paper

3-D Resistance Model for Phase-Change Memory Cell

Article

A Hybrid a-Si and Poly-Si TFTs Technology for AMOLED Pixel Circuits

Article

An Analytic Model for Gate-all-around Silicon Nanowire Tunneling Field Effect Transistors

Article

Analytical Modeling of Capacitances for GaN HEMTs, Including Parasitic Components

Article

Highly Aligned Graphene/Polymer Nanocomposites with Excellent Dielectric Properties for High Performance Electromagnetic Interference Shielding

Article

Implementation of Fully Self-Aligned Homojunction Double-Gate a-IGZO TFTs

Article

Model Order Reduction for Quantum Transport Simulation of Band-To-Band Tunneling Devices

Article

Modeling of Mutual Coupling Between Planar Inductors in Wireless Power Applications

Article

SPICE Modeling of Double-Gate Tunnel-FETs Including Channel Transports

Article

A Channel Potential Based Model for SiO2- Core Si-Shell SRGMOSFET

Conference paper

A gate leakage model for double gate tunneling field-effect transistors

Conference paper

A Low-noise Local Bitline Technique for Dual-Vt Register Files

Conference paper

A new degradation mechanism and its role on negative bias temperature instability in metal-oxide-semiconductor devices

Conference paper

A novel Makowski charge pump and its optimization using Lagrange theorem

Conference paper

A physics based Potential Model for Cylindrical Surrounding Gate MOSFETs with SiO₂-core Si-Shell Structure

Conference paper

A Web-based Education Platform for Nanoscale Device Modeling and Circuit Simulation

Conference paper

An Analytic Model for Nanowire Tunnel-FETs

Conference paper

An Analytic Potential Based Model for Gate-all-around Nanowire Tunnel-FETs

Conference paper

Analytical model of the subthreshold behavior in short-channel junctionless cylindrical surrounding-gate mosfets

Conference paper

Analytical Modeling for AlGaN/GaN HEMTs

Conference paper

Atomic disorder scattering in emerging transistors by parameter-free first principle modeling

Conference paper

Atomistic Simulation of Phase Change Memory During Switching

Conference paper

Bias stress induced threshold voltage instability in solution processed organic thin film transistor

Conference paper

Characteristics of double-gate a-IGZO TFT

Conference paper

Compact modeling beyond device physics

Conference paper

Critical parasitic capacitance in nano-scale phase-change memory (PCM) cell

Conference paper

Developing a common compact modeling platform for model developers and users

Conference paper

Developing a Common Compact Modeling Platform for Model Developers and Users

Conference paper

Developing i-MOS as a Compact Model Standardization Platform

Conference paper

Double-gate tunneling FET with asymmetric gate structure and pocket source

Conference paper

Fabrication and characterization of carbon nanotube interconnect vias for next-generation technology nodes

Conference paper

Impact of Lateral Fin-Width Non-Uniformity of FinFETs

Conference paper

Influence of fin-width lateral variations of a FinFET

Conference paper

Low Voltage SRAM Design using Tunneling Regime of CNTFET

Conference paper

Metal-gate resistance with skin effect consideration in nanoscale MOSFETs for millimeter-wave ICs

Conference paper

Multi-walled carbon nanotube coated microelectrode array for high-throughput, sensitive dopamine detection

Conference paper

Powering the More than Moore Electronics with i-MOS

Conference paper

Research progress on core-shell nanowire FETs

Conference paper

Silicon nanowire metal-oxide-semiconductor field effect transistor NBTI effect modeling and application in circuit performance simulation

Conference paper

Standardizing the Compact Model Developments for Emerging Transistors

Conference paper

Study on nucleation characteristic of phase change memory set operation using numerical simulation

Conference paper

The pathway to develop an industrial standard device model: From device physics to parameter extraction

Conference paper

Using 0-dimensional silica to control diameter and density of carbon nanotubes

Conference paper

A Comparative Study of Ballistic Transport Models for Nanowire MOSFETs

Article

A Nonlinear Poisson-Schrodinger Solver Under Cylindrical Coordinate for Quantum Effect in Nanowire MOSFET

Article

Design and Verification of a High Performance LED Driver with an Efficient Current Sensing Architecture

Article

Effects of Fin Sidewall Angle on Subthreshold Characteristics of Junctionless Multigate Transistors

Article

First Principles Simulations of Nanoscale Silicon Devices With Uniaxial Strain

Article

Non-Charge-Sheet Analytic Model for Ideal Retrograde Doping MOSFETs

Article

Numerical Electron Mobility Model of Nanoscale Symmetric, Asymmetric and Independent Double-Gate MOSFETs

Article

Silicon-Embedded Receiving Coil for High-Efficiency Wireless Power Transfer to Implantable Biomedical ICs

Article

Suppression of tunneling leakage current in junctionless nanowire transistors

Article

Surface acoustic wave resonators based on (002) AlN/Pt/diamond/silicon layered structure

Article

Temperature-compensated high-frequency surface acoustic wave device

Article

Visible-light photoresponse of AlN-based film bulk acoustic wave resonator

Article

Modeling FinFETs for CMOS Applications

Book chapter

Nanoscale Semiconductor Memories Technology and Applications: Chapter 10. Phase-Change Memory Cell Model and Simulation

Book chapter

A 51fA/Hz0.5 Low Power Heterodyne Impedance Analyzer for Electrochemical Impedance Spectroscopy

Conference paper

A DC Model of TFETs for SPICE Simulation

Conference paper

Application of Multi-frequency Test and Neural Network to Fault Diagnosis in Analog Circuits

Conference paper

Effect of Parasitic Capacitances and Resistances on the RF Performance of Nanoscale MOSFETs

Conference paper

First Principle Simulations of the [110] Uniaxial Strain Effects in Electron Transport

Conference paper

Integration of Diamond-like Carbon and AlN for Acoustic Wave Devices

Conference paper

Modeling of an Inductive Link for Wireless Power Applications

Conference paper

Multi-frequency Test for Analog Circuits

Conference paper

Numerical study on effects of random dopant fluctuation in double gate tunneling FET

Conference paper

Numerical study on gate-All-Around tunneling FET with SiO2 core and Si shell structure

Conference paper

Numerical Study on Nanowire Tunnel FET with Dynamic Threshold Operation Architecture

Conference paper

Predicting Key Parameters of Inductive Power Links

Conference paper

Random Dopant Fluctuation Effects on Double Gate Tunneling FET Performance

Conference paper

Strain Modeling in Source Exhaustion Regime of Carbon Nanotube Field Effect Transistor

Conference paper

Study on Dynamic Threshold Nanowire Tunneling FET

Conference paper

32.9 nV/rt Hz-60.6 dB THD Dual-Band Micro-Electrode Array Signal Acquisition IC

Article

A Compact CMOS Compatible Oxide Antifuse With Polysilicon Diode Driver

Article

A Junctionless Nanowire Transistor With a Dual-Material Gate

Article

A unified charge-based model for SOI MOSFETs applicable from intrinsic to heavily doped channel

Article

An Analytical Charge Model for Double-Gate Tunnel FETs

Article

An Explicit Surface Potential Model of Bulk-MOSFETs with Inclusion of Poly-Gate Accumulation, Depletion and Inversion Effects

Article

Gate underlap design for short channel effects control in cylindrical gate-all-around MOSFETs based on an analytical model

Article

Low-Temperature ZnO TFTs Fabricated by Reactive Sputtering of Metallic Zinc Target

Article

Model-Based Prediction of the Plasma Oscillation Excitation Response Characteristics of a High-Electron Mobility Transistor-Based Terahertz Photomixer with the Cap Region

Article

Modeling of the Cell-Electrode Interface Noise for Microelectrode Arrays

Article

One-time-programmable memory in LTPS TFT technology with metal-induced lateral crystallization

Article

Phase-change memory with multifin thin-film-transistor driver technology

Article

Polynomial-Effective-Channel-Mobility-Based Above-Threshold Current Model for Undoped Polycrystalline-Silicon Thin-Film Transistors Consistent With Pao-Sah Model

Article

Reactive Radiofrequency Sputtering-Deposited Nanocrystalline ZnO Thin-Film Transistors

Article

The Use of SU-8 Topographically Guided Microelectrode Array in Measuring Extracellular Field Potential Propagation

Article

Unified Scale Length for Four-Terminal Double-Gate MOSFETs

Article

A charge based non-quasi-static transient model for SOI MOSFETs

Conference paper

A Compact Model for Double-Gate Tunneling Field-Effect-Transistors and Its Implications on Circuit Behaviors

Conference paper

A MATLAB Program for Volterra Distortion Analysis in CMOS Switched Source Follower

Conference paper

An experimental study of Engineering-Science-Mathematics Approach in elementary engineering and science education

Conference paper

Analytical Drain Current Model for Organic Thin-Film Transistors

Conference paper

Building a user friendly infrastructure for compact model development in the nano-device era

Conference paper

Comparison of MEA signals derived from peritoneal mast cells and RBL-2H3 cells

Conference paper

Fault Diagnosis of Analog Circuits Based on Multi-frequency Test and Neural Network Method

Conference paper

Field-Based 3D Capacitance Modeling for sub-45-nm On-Chip Interconnect

Conference paper

Field-Based Parasitic Capacitance Models for 2D and 3D sub-45-nm Interconnect

Conference paper

Geometry based resistance model for phase change memory

Conference paper

i-MOS: A platform for compact model sharing

Conference paper

Investigations of fin vertical nonuniformity effects on junctionless multigate transistor

Conference paper

Modeling of mutual inductance for planar inductors used in inductive link applications

Conference paper

Numerical Study on Dual Material Gate Nanowire Tunnel Field-Effect Transistor

Conference paper

Reduction of ambipolarity in carbon nanotube field-effect transistor by non-uniform source/drain doping and increased extension length

Conference paper

Simulation on Random Dopant Fluctuation Effect Impact on Double Gate MOSFET and Corresponding 6-T SRAM Performance

Conference paper

Wireless power link design using silicon-embedded inductors for brain-machine interface

Conference paper

3-D Numerical Simulation Study on 20 nm NMOSFET Design

Article

A rigorous and concise surface potential-based core model for the undoped symmetric double-gate metal-oxide-semiconductor field effect transistors

Article

Cardioprotective Effects of Potassium Channel Openers on Rat Atria and Isolated Hearts under Acute Hypoxia

Article

Computation Efficient Yet Accurate Surface Potential Based Analytic Model for Symmetric DG MOSFETs to Predict Current-Voltage Characteristics

Article

Driving Device Comparison for Phase-Change Memory

Article

Highly accurate dual-band cellular field potential acquisition for brain-machine interface

Article

Modeling Short-Channel Effect of Elliptical Gate-All-Around MOSFET by Effective Radius

Article

Phase-Change Memory RESET Model Based on Detailed Cell Cooling Profile

Article

The Significance of Chloride in the Inhibitory Action of Disodium Cromoglycate on Immunologically-stimulated Rat Peritoneal Mast Cells

Article

Uniaxial Strain Effects on Electron Ballistic Transport in Gate-All-Around Silicon Nanowire MOSFETs

Article

Zero-Mask Contact Fuse for One-Time-Programmable Memory in Standard CMOS Processes

Article

A 38.6nV/Hz(0.5)-59.6dB THD Dual-Band Micro-Electrode Array Signal Acquisition IC

Conference paper

A phase-change random access memory model for circuit simulation

Conference paper

A Unified Drain Current Model for Nanoscale Double-Gate and Surrounding-Gate MOSFETs Incorporating Velocity Saturation

Conference paper

An Oxide/Silicon Core/Shell Nanowire FET

Conference paper

Comparison and insight into long-channel MOSFET drain current models

Conference paper

Cross-Section Control of Stacked Nanowires Formed by Bosch Process and Oxidation

Conference paper

i-MOS.org - interactive Modeling and Online Simulation platform for compact modeling

Conference paper

Nonparabolicity effects of the ultra-thin body double-gate MOSFETs

Conference paper

Phase-change memory on thin-film-transistor technology

Conference paper

Predicting Key Features of Double-Gate Tunnel FETs

Conference paper

Vertical Non-uniformity Effect on FinFET Performance Characteristics

Conference paper

A generic numerical model for detection of terahertz radiation in MOS field-effect transistors

Article

A noncharge-sheet channel potential and drain current model for dynamic-depletion silicon-on-insulator metal-oxide-semiconductor field-effect transistors

Article

A Study of the Relationship Between Pharmacologic Preconditioning and Adenosine Triphosphate-Sensitive Potassium (K-ATP) Channels on Cultured Cardiomyocytes Using the Microelectrode Array

Article

A system-on-chip EPC Gen-2 passive UHF RFID tag with embedded temperature sensor

Article

Analytical solution of subthreshold channel potential of gate underlap cylindrical gate-all-around MOSFET

Article

Charge-based model for symmetric double-gate MOSFETs with inclusion of channel doping effect

Article

Comparison of electrical stress-induced charge carrier generation/trapping and related degradation of SiO 2 and HfO 2/SiO 2 gate dielectric stacks

Article

Continuous surface potential versus voltage equation of intrinsic surrounding-gate MOSFETs and analytic solution from accumulation to strong inversion region

Article

Diode parameter extraction by a linear cofactor difference operation method

Article

Generic Compact Model of Double-Gate MOSFETs Applicable to Different Operation Modes and Channels

Article

Introduction to the Special Section on Electronic and Ionic Interfaces to Biomolecules and Cells

Article

Numerical Simulation of Detection Response of Field Effect MOS Transistor to Modulated Terahertz Radiation Signal

Article

Silicon-based nanowire MOSFETs: from process and device physics to simulation and modeling

Book chapter

3-D matrix nano-wire transistor fabrication on silicon substrate

Conference paper

A high power switch-mode LED driver with an efficient current sensing scheme

Conference paper

A Potential-based Analytic Model for Monocrystalline Silicon Thin-film Transistors on Glass Substrates

Conference paper

A system-on-chip EPC Gen-2 passive UHF RFID tag with embedded temperature sensor

Conference paper

A Unified Drain Current Model for Nanoscale Double-Gate and Surrounding-Gate MOSFETs Incorporating Velocity Saturation

Conference paper

Analytical subthreshold channel potential model of asymmetric gate underlap gate-all-around MOSFET

Conference paper

Bandstructures of Unstrained and Strained Silicon Nanowire

Conference paper

Characteristics of subband current ratio in double-gate MOSFET

Conference paper

Correlation between gated-diode R-G current and performance degradation of SOI n-MOSFETs after F-N stress test

Conference paper

Cross-section control of stacked nanowires formed by bosch process and oxidation

Conference paper

Determination of unidirectional field potential propagation using MEA chips with topographical guidance

Conference paper

RESET modeling of PCM using thermal budget approach

Conference paper

Submicron MILC TFT performance enhancement by crystallization after patterning

Conference paper

The impact of device parameter variation on double gate tunneling FET and double gate MOSFET

Conference paper

To Characterise The Membrane Field Potential Changes Following Non-Immunological and Immunological Activations Of Rat Peritoneal Mast Cells

Conference paper

Two-transistor active pixel image sensor with active diode reset

Conference paper

A charge-based compact model for predicting the current-voltage and capacitance-voltage characteristics of heavily doped cylindrical surrounding-gate MOSFETs

Article

A complete analytic surface potential-based core model for intrinsic nanowire surrounding-gate MOSFETs

Article

A continuous surface-potential solution from accumulation to inversion for intrinsic symmetric double-gate MOSFETs

Article

A multi-stage low-dropout regulator with 1 pF compensation capacitor for System-on-Chip applications

Article

A surface potential-based non-charge-sheet core model for undoped surrounding-gate MOSFETs

Article

Effects of body doping on threshold voltage and channel potential of symmetric DG MOSFETs with continuous solution from accumulation to strong-inversion regions

Article

Electrical stress-induced charge carrier generation/trapping related degradation of HfAlO/SiO2 and HfO2/SiO2 gate dielectric stacks

Article

Mechanism of positive charge generation in the bulk of HfAlO/SiO2 stack

Article

Modulatory action of potassium channel openers on field potential and histamine release from rat peritoneal mast cells

Article

Sub-threshold behavior of long channel undoped cylindrical surrounding-gate MOSFETs

Article

Terahertz Wave Generation and Detection Analysis of Silicon Nanowire MOS Field-Effect Transistor

Article

The use of microelectrode array (MEA) to study the protective effects of potassium channel openers on metabolically compromised HL-1 cardiomyocytes

Article

To establish a pharmacological experimental platform for the study of cardiac hypoxia using the microelectrode array

Article

Vertically Stacked Silicon Nanowire Transistors Fabricated by Inductive Plasma Etching and Stress-Limited Oxidation

Article

A unified FinFET reliability model including high K gate stack dynamic threshold voltage, hot carrier injection, and negative bias temperature instability

Conference paper

A web-based platform for nanoscale non-classical device modeling and circuit performance simulation

Conference paper

An analytic model of the silicon-based nanowire Schottky Barrier MOSFET

Conference paper

Characterisation of the Effects of Calcium Channel Blockers and Potassium Channel Openers on HL-1 Cardiomyocytes Using the Microelectrode Array

Conference paper

Computation efficient yet accurate surface potential based analytic model for symmetric DG MOSFETs to predict current-voltage characteristics

Conference paper

Diode Based Gate Oxide Anti-fuse One Time Programmable Memory Array in Standard CMOS Process

Conference paper

Generic compact model development of double-gate MOSFETs with inclusion of different operation modes and channels from heavily doped to intrinsic case

Conference paper

Modeling of hole generation/trapping in ultrathin SiO₂ films during gate injection of electrons in direct tunneling regime

Conference paper

Numerical Simulation of Programming and Read Process for Nano-Scale Phase-Change Memory (PCM) Cell

Conference paper

SET and RESET State Resistance Modeling of Phase Change Memory

Conference paper

A 0.9-V input discontinuous-conduction-mode boost converter with CMOS-control rectifier

Article

A Compact Model of Silicon-Based Nanowire MOSFETs for Circuit Simulation and Design

Article

A Non-Charge-Sheet Analytic Model for Symmetric Double-Gate MOSFETs With Smooth Transition Between Partially and Fully Depleted Operation Modes

Article

A novel source/drain on void (SDOV) MOSFET implemented by local co-implantation of hydrogen and helium

Article

A rigorous carrier-based analytic model for undoped ultra-thin-body silicon-on-insulator (UTB-SOI) MOSFETs

Article

An explicit carrier-based compact model for nanowire surrounding-gate MOSFET simulation

Article

An explicit surface-potential-based model for undoped double-gate MOSFETs

Article

Charge-based model for long-channel cylindrical surrounding-gate MOSFETs from intrinsic channel to heavily doped body

Article

Development of single-transistor-control LDO based on flipped voltage follower for SoC

Article

FinFET reliability study by forward gated-diode generation-recombination current

Article

Full-band quantum transport based simulation for carbon nanotube field effect transistor from chirality to device performance

Article

Generic carrier-based core model for undoped four-terminal double-gate MOSFETs valid for symmetric, asymmetric, and independent-gate-operation modes

Article

Silicon oxynitride integrated waveguide for on-chip optical interconnects applications

Article

The use of microelectrode array (MEA) to study rat peritoneal mast cell activation

Article

Stacked CMOS Technologies

Book chapter

A charge-based compact model for arbitrary doped cylindrical surrounding-gate MOSFETs

Conference paper

A CMOS Active-Pixel Sensor Based DNA Micro-Array with Nano-Metallic Particles Detection Protocol

Conference paper

A Complete Analytic Surface Potential-Based Core Model for Undoped Cylindrical Surrounding-Gate MOSFETs

Conference paper

A complete charge based compact model for silicon nanowire FETs including doping and advanced physical effects

Conference paper