PhD in Electronic and Computer Engineering
The Hong Kong University of Science and Technology, 2016
Conference paper
A 1.2V-to-0.4V 3.2GHz-to-14.3MHz Power-Efficient 3-Port Register File in 65-nm CMOS
Article
A 140mV Variation-Tolerant Deep Sub-Threshold SRAM in 65nm CMOS
Article
A Voltage-Scalable Zero-Delay-Overhead Scheme for Standby Power Reduction in Dynamic Register Files
Conference paper
Article
Modeling CNTFET Performance Variation due to Spatial Distribution of Carbon Nanotubes
Article
Modeling spatial distribution induced variability in CNT array based FETs
Conference paper
A 65nm 3.2GHz 44.2mW Low-Vt Register File with Robust Low-capacitance Dynamic Local Bitlines
Conference paper
An Area-Efficient 1.5-GHz Dual-VDD 4-Port Register File for Real-Time Microprocessors
Conference paper
Nanoscale Register File Circuit Design – Challenges and Opportunities
Conference paper
Write Ability Enhancement Techniques for L1 Cache on Next-Generation IBM POWERTM Processors
Conference paper
A Low-noise Local Bitline Technique for Dual-Vt Register Files
Conference paper
Low Voltage SRAM Design using Tunneling Regime of CNTFET
Conference paper
Characterization of a Low Leakage Current and High-speed 7T SRAM Circuit with Wide Voltage Margins
Conference paper
A novel low-leakage 8T differential SRAM cell
Conference paper
Comparison of two SRAM matrix leakage reduction techniques in 45nm technology
Conference paper
Modeling spatial distribution induced variability in CNT array based FETs
A 65nm 3.2GHz 44.2mW Low-Vt Register File with Robust Low-capacitance Dynamic Local Bitlines
An Area-Efficient 1.5-GHz Dual-VDD 4-Port Register File for Real-Time Microprocessors
Nanoscale Register File Circuit Design – Challenges and Opportunities
Write Ability Enhancement Techniques for L1 Cache on Next-Generation IBM POWERTM Processors
A 1.2V-to-0.4V 3.2GHz-to-14.3MHz Power-Efficient 3-Port Register File in 65-nm CMOS
Article
A 140mV Variation-Tolerant Deep Sub-Threshold SRAM in 65nm CMOS
Article
A Voltage-Scalable Zero-Delay-Overhead Scheme for Standby Power Reduction in Dynamic Register Files
Conference paper
Article
Modeling CNTFET Performance Variation due to Spatial Distribution of Carbon Nanotubes
Article
Modeling spatial distribution induced variability in CNT array based FETs
Conference paper
A 65nm 3.2GHz 44.2mW Low-Vt Register File with Robust Low-capacitance Dynamic Local Bitlines
Conference paper
An Area-Efficient 1.5-GHz Dual-VDD 4-Port Register File for Real-Time Microprocessors
Conference paper
Nanoscale Register File Circuit Design – Challenges and Opportunities
Conference paper
Write Ability Enhancement Techniques for L1 Cache on Next-Generation IBM POWERTM Processors
Conference paper
A Low-noise Local Bitline Technique for Dual-Vt Register Files
Conference paper
Low Voltage SRAM Design using Tunneling Regime of CNTFET
Conference paper
Characterization of a Low Leakage Current and High-speed 7T SRAM Circuit with Wide Voltage Margins
Conference paper
A novel low-leakage 8T differential SRAM cell
Conference paper
Comparison of two SRAM matrix leakage reduction techniques in 45nm technology
Conference paper
No Publications |
No Publications |
No Publications |
No Publications |
EESM5000 | CMOS VLSI Design |
ELEC4410 | CMOS VLSI Design |
CPEG4911 | Computer Engineering Final Year Project in ELEC |
EESM5020 | Digital VLSI System Design and Design Automation |
EESM6980M | MSc Project |
ELEC3910 | Academic and Professional Development II |
ELEC4900 | Final Year Design Project |
ELEC5160 | Digital VLSI System Design and Design Automation |
EESM6980M | MSc Project |
EESM5000 | CMOS VLSI Design |
ELEC3910 | Academic and Professional Development II |
ELEC4410 | CMOS VLSI Design |
No Teaching Assignments |
No Teaching Assignments |
ZHANG, Ce
(co-supervision)
Electronic and Computer Engineering
SHAH, Ikramullah
(co-supervision)
Electronic and Computer Engineering
ZHENG, Huimin
(co-supervision)
Electronic and Computer Engineering
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