Lecturer I
Department of Electronic and Computer Engineering
Khawar SARFRAZ
PhD in Electronic and Computer Engineering
The Hong Kong University of Science and Technology, 2016
Research Interest
- Very large-scale integration (VLSI)
- Integrated circuits and systems
- Mixed-signal / analog integrated circuit (IC)
- Internet of Things (IoT)
- Artificial intelligence
Publications
2021 1
Conference paper
2017 3
A 1.2V-to-0.4V 3.2GHz-to-14.3MHz Power-Efficient 3-Port Register File in 65-nm CMOS
Article
A 140mV Variation-Tolerant Deep Sub-Threshold SRAM in 65nm CMOS
Article
A Voltage-Scalable Zero-Delay-Overhead Scheme for Standby Power Reduction in Dynamic Register Files
Conference paper
2016 3
Article
Modeling CNTFET Performance Variation due to Spatial Distribution of Carbon Nanotubes
Article
Modeling spatial distribution induced variability in CNT array based FETs
Conference paper
2015 4
A 65nm 3.2GHz 44.2mW Low-Vt Register File with Robust Low-capacitance Dynamic Local Bitlines
Conference paper
An Area-Efficient 1.5-GHz Dual-VDD 4-Port Register File for Real-Time Microprocessors
Conference paper
Nanoscale Register File Circuit Design – Challenges and Opportunities
Conference paper
Write Ability Enhancement Techniques for L1 Cache on Next-Generation IBM POWERTM Processors
Conference paper
2014 2
A Low-noise Local Bitline Technique for Dual-Vt Register Files
Conference paper
Low Voltage SRAM Design using Tunneling Regime of CNTFET
Conference paper
2013 1
Characterization of a Low Leakage Current and High-speed 7T SRAM Circuit with Wide Voltage Margins
Conference paper
2011 1
A novel low-leakage 8T differential SRAM cell
Conference paper
2010 1
Comparison of two SRAM matrix leakage reduction techniques in 45nm technology
Conference paper
Conference paper 1
Modeling spatial distribution induced variability in CNT array based FETs
Conference paper 4
A 65nm 3.2GHz 44.2mW Low-Vt Register File with Robust Low-capacitance Dynamic Local Bitlines
An Area-Efficient 1.5-GHz Dual-VDD 4-Port Register File for Real-Time Microprocessors
Nanoscale Register File Circuit Design – Challenges and Opportunities
Write Ability Enhancement Techniques for L1 Cache on Next-Generation IBM POWERTM Processors
Conference paper 1
2017 3
A 1.2V-to-0.4V 3.2GHz-to-14.3MHz Power-Efficient 3-Port Register File in 65-nm CMOS
Article
A 140mV Variation-Tolerant Deep Sub-Threshold SRAM in 65nm CMOS
Article
A Voltage-Scalable Zero-Delay-Overhead Scheme for Standby Power Reduction in Dynamic Register Files
Conference paper
2016 3
Article
Modeling CNTFET Performance Variation due to Spatial Distribution of Carbon Nanotubes
Article
Modeling spatial distribution induced variability in CNT array based FETs
Conference paper
2015 4
A 65nm 3.2GHz 44.2mW Low-Vt Register File with Robust Low-capacitance Dynamic Local Bitlines
Conference paper
An Area-Efficient 1.5-GHz Dual-VDD 4-Port Register File for Real-Time Microprocessors
Conference paper
Nanoscale Register File Circuit Design – Challenges and Opportunities
Conference paper
Write Ability Enhancement Techniques for L1 Cache on Next-Generation IBM POWERTM Processors
Conference paper
2014 2
A Low-noise Local Bitline Technique for Dual-Vt Register Files
Conference paper
Low Voltage SRAM Design using Tunneling Regime of CNTFET
Conference paper
2013 1
Characterization of a Low Leakage Current and High-speed 7T SRAM Circuit with Wide Voltage Margins
Conference paper
2011 1
A novel low-leakage 8T differential SRAM cell
Conference paper
2010 1
Comparison of two SRAM matrix leakage reduction techniques in 45nm technology
Conference paper
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| No Publications |
| No Publications |
| No Publications |
Teaching Assignment
| EESM5020 | Digital VLSI System Design and Design Automation |
| EESM6970 | Guided Chip Design Project |
| ELEC5160 | Digital VLSI System Design and Design Automation |
| EESM6970 | Guided Chip Design Project |
| EESM5000 | CMOS VLSI Design |
| ELEC4410 | CMOS VLSI Design |
| CPEG4911 | Computer Engineering Final Year Project in ELEC |
| EESM5020 | Digital VLSI System Design and Design Automation |
| EESM6980M | MSc Project |
| ELEC3910 | Academic and Professional Development II |
| ELEC4900 | Final Year Design Project |
| ELEC5160 | Digital VLSI System Design and Design Automation |
| EESM6980M | MSc Project |
| No Teaching Assignments |
Research Postgraduate (RPG) Supervision
From January 2022 to December 2025 (As of 03 April 2025)
Current RPGs
Doctor of Philosophy
-
ZHANG, Ce (co-supervision)
Electronic and Computer Engineering -
SHAH, Ikramullah (co-supervision)
Electronic and Computer Engineering
Master of Philosophy
-
ZHENG, Huimin (co-supervision)
Electronic and Computer Engineering