CV-CIM: A Hybrid Domain Xor-Derived Similarity-Aware Computation-in-Memory Supporting Cost-Volume Construction

DyBit: Dynamic Bit-Precision Numbers for Efficient Quantized Neural Network Inference

HDSuper: High-Quality and High Computational Utilization Edge Super-Resolution Accelerator With Hardware-Algorithm Co-Design Techniques

SWG: an architecture for sparse weight gradient computation

TensorCIM: Digital Computing-in-Memory Tensor Processor With Multichip-Module-Based Architecture for Beyond-NN Acceleration

Towards efficient generative AI and beyond-AI computing: New trends on ISSCC 2024 machine learning accelerators

15.1 A 0.795fJ/bit Physically-Unclonable Function-Protected TCAM for a Software-Defined Networking Switch

20.2 A 28nm 74.34TFLOPS/W BF16 Heterogenous CIM-Based Accelerator Exploiting Denoising-Similarity for Diffusion Models

A 28nm 4170-TFLOPS/W/b and 195-TFLOPS/mm²/b Multiply-Free Fully-Digital Floating-Point Compute-In-Memory Macro with Mitchell's Approximation

AdaP-CIM: Compute-in-Memory Based Neural Network Accelerator using Adaptive Posit

ETCIM: An Error-Tolerant Digital-CIM Processor with Redundancy-Free Repair and Run-Time MAC and Cell Error Correction

Exploiting Similarity Opportunities of Emerging Vision AI Models on Hybrid Bonding Architecture

Multi-Issue Butterfly Architecture for Sparse Convex Quadratic Programming

MulTCIM: Digital Computing-in-Memory-Based Multimodal Transformer Accelerator With Attention-Token-Bit Hybrid Sparsity

Reconfigurability, Why It Matters in AI Tasks Processing: A Survey of Reconfigurable AI Chips

ReDCIM: Reconfigurable Digital Computing-in-Memory Processor with Unified FP/INT Pipeline for Cloud AI Acceleration

SDP: Co-Designing Algorithm, Dataflow, and Architecture for In-SRAM Sparse NN Acceleration

SPCIM: Sparsity-Balanced Practical CIM Accelerator with Optimized Spatial-Temporal Multi-Macro Utilization

STAR: An STGCN ARchitecture for Skeleton-Based Human Action Recognition

TranCIM: Full-Digital Bitline-Transpose CIM-based Sparse Transformer Accelerator With Pipeline/Parallel Reconfigurable Modes

16.1 MuITCIM: A 28nm 2.24 μ J Token Attention-Token-Bit Hybrid Sparse Digital CIM-Based Accelerator for Multimodal Transformers

16.4 TensorCIM: A 28nm 3.7nJ/Gather and 8.3TFLOPS/W FP32 Digital-CIM Tensor Processor for MCM-CIM-Based Beyond-NN Acceleration

AutoDCIM: An Automated Digital CIM Compiler

BIOS: A 40nm Bionic Sensor-defined 0.47pJ/SOP, 268.7TSOPs/W Configurable Spiking Neuron-in-Memory Processor for Wearable Healthcare

ECSSD: Hardware/Data Layout Co-Designed In-Storage-Computing Architecture for Extreme Classification

PIM-HLS: An Automatic Hardware Generation Tool for Heterogeneous Processing-In-Memory-based Neural Network Accelerators

SPG: Structure-Private Graph Database via SqueezePIR

Towards Efficient Control Flow Handling in Spatial Architecture via Architecting the Control Flow Plane

Dynamic Sparse Attention for Scalable Transformer Acceleration

GQNA: Generic Quantized DNN Accelerator With Weight-Repetition-Aware Activation Aggregating

H2Learn: High-Efficiency Learning Accelerator for High-Accuracy Spiking Neural Networks

A 28nm 15.59J/Token Full-Digital Bitline-Transpose CIM-Based Sparse Transformer Accelerator with Pipeline/Parallel Reconfigurable Modes

A 28nm 29.2TFLOPS/W BF16 and 36.5TOPS/W INT8 Reconfigurable Digital CIM Processor with Unified FP/INT Pipeline and Bitwise In-Memory Booth Multiplication for Cloud Deep Learning Acceleration

Accelerating Spatiotemporal Supervised Training of Large-Scale Spiking Neural Networks on GPU

Alleviating datapath conflicts and design centralization in graph analytics acceleration

DOTA: Detect and OmitWeak Attentions for Scalable Transformer Acceleration

INSPIRE: IN-Storage Private Information REtrieval via Protocol and Architecture Co-design

Evolver: A Deep Learning Processor with On-Device Quantization-Voltage-Frequency Tuning

ADROIT: An Adaptive Dynamic Refresh Optimization Framework for DRAM Energy Saving in DNN Training

Brain-Inspired Computing: Adventure from Beyond CMOS Technologies to Beyond von Neumann Architectures

DUET: Boosting deep neural network efficiency on dual-module architecture

STC: Significance-aware transform-based codec framework for external memory access reduction

A High Throughput Acceleration for Hybrid Neural Networks with Efficient Resource Management on FPGA

Parana: A Parallel Neural Architecture Considering Thermal Problem of 3D Stacked Memory

Reconfigurable Architecture for Neural Approximation in Multimedia Computing

Towards Efficient Compact Network Training on Edge-Devices

A High Energy Efficient Reconfigurable Hybrid Neural Network Processor for Deep Learning Applications

GNA: Reconfigurable and efficient architecture for generative network acceleration

LCP: A Layer Clusters Paralleling mapping method for accelerating Inception and Residual networks on FPGA

RANA: Towards efficient neural acceleration with refresh-Optimized embedded DRAM

Deep Convolutional Neural Network Architecture with Reconfigurable Computation Patterns

A 1.06-to-5.09 TOPS/W reconfigurable hybrid-neural-network processor for deep learning applications

Neural approximating architecture targeting multiple application domains

RNA: A reconfigurable architecture for hardware neural acceleration

A High Throughput Acceleration for Hybrid Neural Networks with Efficient Resource Management on FPGA

Article

Parana: A Parallel Neural Architecture Considering Thermal Problem of 3D Stacked Memory

Article

Reconfigurable Architecture for Neural Approximation in Multimedia Computing

Article

Towards Efficient Compact Network Training on Edge-Devices

Conference paper

A High Energy Efficient Reconfigurable Hybrid Neural Network Processor for Deep Learning Applications

Article

GNA: Reconfigurable and efficient architecture for generative network acceleration

Article

LCP: A Layer Clusters Paralleling mapping method for accelerating Inception and Residual networks on FPGA

Conference paper

RANA: Towards efficient neural acceleration with refresh-Optimized embedded DRAM

Conference paper

Deep Convolutional Neural Network Architecture with Reconfigurable Computation Patterns

Article

A 1.06-to-5.09 TOPS/W reconfigurable hybrid-neural-network processor for deep learning applications

Conference paper

Neural approximating architecture targeting multiple application domains

Conference paper

RNA: A reconfigurable architecture for hardware neural acceleration

Conference paper