DEng in Electronic Science and Technology
Tsinghua University, 2019
DyBit: Dynamic Bit-Precision Numbers for Efficient Quantized Neural Network Inference
Article
Article
SWG: an architecture for sparse weight gradient computation
Article
Article
Article
Conference paper
Conference paper
Conference paper
AdaP-CIM: Compute-in-Memory Based Neural Network Accelerator using Adaptive Posit
Conference paper
Conference paper
Exploiting Similarity Opportunities of Emerging Vision AI Models on Hybrid Bonding Architecture
Conference paper
Multi-Issue Butterfly Architecture for Sparse Convex Quadratic Programming
Conference paper
Article
Reconfigurability, Why It Matters in AI Tasks Processing: A Survey of Reconfigurable AI Chips
Article
Article
SDP: Co-Designing Algorithm, Dataflow, and Architecture for In-SRAM Sparse NN Acceleration
Article
Article
STAR: An STGCN ARchitecture for Skeleton-Based Human Action Recognition
Article
Article
Conference paper
Conference paper
AutoDCIM: An Automated Digital CIM Compiler
Conference paper
Conference paper
ECSSD: Hardware/Data Layout Co-Designed In-Storage-Computing Architecture for Extreme Classification
Conference paper
Conference paper
SPG: Structure-Private Graph Database via SqueezePIR
Conference paper
Conference paper
Dynamic Sparse Attention for Scalable Transformer Acceleration
Article
GQNA: Generic Quantized DNN Accelerator With Weight-Repetition-Aware Activation Aggregating
Article
H2Learn: High-Efficiency Learning Accelerator for High-Accuracy Spiking Neural Networks
Article
Conference paper
Conference paper
Accelerating Spatiotemporal Supervised Training of Large-Scale Spiking Neural Networks on GPU
Conference paper
Alleviating datapath conflicts and design centralization in graph analytics acceleration
Conference paper
DOTA: Detect and OmitWeak Attentions for Scalable Transformer Acceleration
Conference paper
INSPIRE: IN-Storage Private Information REtrieval via Protocol and Architecture Co-design
Conference paper
Evolver: A Deep Learning Processor with On-Device Quantization-Voltage-Frequency Tuning
Article
ADROIT: An Adaptive Dynamic Refresh Optimization Framework for DRAM Energy Saving in DNN Training
Conference paper
Conference paper
DUET: Boosting deep neural network efficiency on dual-module architecture
Conference paper
STC: Significance-aware transform-based codec framework for external memory access reduction
Conference paper
A High Throughput Acceleration for Hybrid Neural Networks with Efficient Resource Management on FPGA
Article
Parana: A Parallel Neural Architecture Considering Thermal Problem of 3D Stacked Memory
Article
Reconfigurable Architecture for Neural Approximation in Multimedia Computing
Article
Towards Efficient Compact Network Training on Edge-Devices
Conference paper
Article
GNA: Reconfigurable and efficient architecture for generative network acceleration
Article
Conference paper
RANA: Towards efficient neural acceleration with refresh-Optimized embedded DRAM
Conference paper
Deep Convolutional Neural Network Architecture with Reconfigurable Computation Patterns
Article
A 1.06-to-5.09 TOPS/W reconfigurable hybrid-neural-network processor for deep learning applications
Conference paper
Neural approximating architecture targeting multiple application domains
Conference paper
RNA: A reconfigurable architecture for hardware neural acceleration
Conference paper
Reconfigurability, Why It Matters in AI Tasks Processing: A Survey of Reconfigurable AI Chips
SDP: Co-Designing Algorithm, Dataflow, and Architecture for In-SRAM Sparse NN Acceleration
STAR: An STGCN ARchitecture for Skeleton-Based Human Action Recognition
Dynamic Sparse Attention for Scalable Transformer Acceleration
GQNA: Generic Quantized DNN Accelerator With Weight-Repetition-Aware Activation Aggregating
H2Learn: High-Efficiency Learning Accelerator for High-Accuracy Spiking Neural Networks
Accelerating Spatiotemporal Supervised Training of Large-Scale Spiking Neural Networks on GPU
Alleviating datapath conflicts and design centralization in graph analytics acceleration
DOTA: Detect and OmitWeak Attentions for Scalable Transformer Acceleration
INSPIRE: IN-Storage Private Information REtrieval via Protocol and Architecture Co-design
A High Throughput Acceleration for Hybrid Neural Networks with Efficient Resource Management on FPGA
Parana: A Parallel Neural Architecture Considering Thermal Problem of 3D Stacked Memory
Reconfigurable Architecture for Neural Approximation in Multimedia Computing
Article
GNA: Reconfigurable and efficient architecture for generative network acceleration
Article
Conference paper
RANA: Towards efficient neural acceleration with refresh-Optimized embedded DRAM
Conference paper
Deep Convolutional Neural Network Architecture with Reconfigurable Computation Patterns
Article
A 1.06-to-5.09 TOPS/W reconfigurable hybrid-neural-network processor for deep learning applications
Conference paper
Neural approximating architecture targeting multiple application domains
Conference paper
RNA: A reconfigurable architecture for hardware neural acceleration
Conference paper
ELEC3910 | Academic and Professional Development II |
ELEC6910H | Advanced AI Chip and System |
ELEC2350 | Introduction to Computer Organization and Design |
ELEC2910 | Academic and Professional Development I |
ELEC4940C | Independent Study |
ELEC4940F | Independent Study |
ELEC6950A | Departmental Seminar |
ELEC6950B | Departmental Seminar |
ELEC2910 | Academic and Professional Development I |
No Teaching Assignments |
No Teaching Assignments |
No Teaching Assignments |
YAN, Longke
Electronic and Computer Engineering
YANG, Bohan
Electronic and Computer Engineering
ZHAO, Xin
Electronic and Computer Engineering
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