A Flexible Thin-Film Inductor for High-Efficiency Wireless Power Transfer

RVComp: Analog Variation Compensation for RRAM-Based in-Memory Computing

A 10T Soft-Error-Immune SRAM with Multi-node Upset Recovery for Low-Power Space Applications

Energy-Efficient Dual-Node-Upset-Recoverable 12T SRAM for Low-Power Aerospace Applications

Soft-Error-Aware Read-Stability-Enhanced Low-Power 12T SRAM With Multi-Node Upset Recoverability for Aerospace Applications

Tight Compression: Compressing CNN Through Fine-Grained Pruning and Weight Permutation for Efficient Implementation

A 16-bit Encrypted On-chip Embedded System for Implantable Medical Devices

Design Strategy of Off-Resonant Tertiary Coils for Uplink Detection in Biomedical Implants

FedDQ: Communication-Efficient Federated Learning with Descending Quantization

TAC-RAM: A 65nm 4Kb SRAM Computing-in-Memory Design with 57.55 TOPS/W supporting Multibit Matrix-Vector Multiplication for Binarized Neural Network

Electrical stimulation at nanoscale topography boosts neural stem cell neurogenesis through the enhancement of autophagy signaling

A 40.68-MHz Active Rectifier With Hybrid Adaptive On/Off Delay-Compensation Scheme for Biomedical Implantable Devices

A 6.78-MHz Single-Stage Wireless Charger With Constant-Current Constant-Voltage Charging Technique

A Fully Dynamic Multi-Mode CMOS Vision Sensor With Mixed-Signal Cooperative Motion Sensing and Object Segmentation for Adaptive Edge Computing

A Low-Power Motion Estimation Architecture for HEVC based on a New Sum of Absolute Difference Computation

Construction of Multi-Kernel Polar Codes with Kernel Substitution

Design of a Single-Stage Wireless Charger with 92.3%-Peak-Efficiency for Portable Devices Applications

Tight compression: Compressing CNN model tightly through unstructured pruning and simulated annealing based permutation

A Low Power Relaxation Oscillator with Switched-Capacitor Frequency-Locked Loop for Wireless Sensor Node Applications

A New Rate-Complexity-Distortion Model for Fast Motion Estimation Algorithm in HEVC

A-12.3 dBm UHF Passive RFID Sense Tag for Grid Thermal Monitoring

Design of Sub-Gigahertz Reconfigurable RF Energy Harvester From-22 to 4 dBm With 99.8% Peak MPPT Power Efficiency

Dual transduction on a single sensor for gas identification

SubMac: Exploiting the subword-based computation in RRAM-based CNNaccelerator for energy saving and speedup

A 2.2μW 600kHz Frequency-Locked Relaxation Oscillator with 0.046%/V Voltage and 48.69ppm/°C Temperature Stability for IoT Sensor Node Applications

A 40.68MHz Active Rectifier with Hybrid Delay Compensation Scheme

A 6.78MHz 92.3%-Peak-Efficiency Single-Stage Wireless Charger with CC-CV Charging and On-Chip Bootstrapping Techniques

A Simplified PWM Controller for Wireless Power Receiver Using a 3-Mode Reconfigurable Resonant Regulating Rectifier

A Two-Staged Adaptive Successive Cancellation List Decoding for Polar Codes

CompRRAE: RRAM-based convolutional neural network accelerator with reduced computations through a runtime activation estimation

Polyimide-Based Flexible 3-Coil Inductive Link Design and Optimization

Single-Stage Rectifying Constant-Current Constant-Voltage Charger for Wireless Charging

A 10.6 pJ·K² Resolution FoM Temperature Sensor Using Astable Multivibrator

A High-Throughput Architecture of List Successive Cancellation Polar Codes Decoder With Large List Size

A low-power compression-based CMOS image sensor with microshift-guided SAR ADC

Analysis and Design of a Ripple Reduction Chopper Bandpass Amplifier

Dual Transduction Surface Acoustic Wave Gas Sensor for VOC Discrimination

Efficient Partial-Sum Network Architectures for List Successive-Cancellation Decoding of Polar Codes

Microshift: An Efficient Image Compression Algorithm for Hardware

Ultra-Low-Power Smart Electronic Nose System Based on Three-Dimensional Tin Oxide Nanotube Arrays

A 2PJ/Pixel/Direction MIMO Processing Based CMOS Image Sensor for Omnidirectional Local Binary Pattern Extraction and Edge Detection

A fully integrated analog front end for biopotential signal sensing

A High-Throughput and Energy-Efficient RRAM-based Convolutional Neural Network using Data Encoding and Dynamic Quantization

An Indoor Solar Energy Harvester with Ultra-Low-Power Reconfigurable Power-On-Reset-Styled Voltage Detector

High Performance High Density Gas-FET Array in Standard CMOS

On Path Memory in List Successive Cancellation Decoder of Polar Codes

Room-Temperature Dual-Mode CMOS Gas-FET Sensor for Diabetes Detection

Sparsenn: An energy-efficient neural network accelerator exploiting input and output sparsity

Ultra-Low Power Smart Electronic Nose System Based on Three-Dimensional Tin-Oxide Nanotube Arrays for Multiple Gases and Mixture Detection

A 6.78-MHz Single-Stage Wireless Power Receiver Using a 3-Mode Reconfigurable Resonant Regulating Rectifier

Chopper Capacitively-Coupled Instrumentation Amplifier Capable of Handling Large Electrode Offset for Biopotential Recordings

High-Throughput and Energy-Efficient Belief Propagation Polar Code Decoder

Optic Nerve Stimulation System with Adaptive Wireless Powering and Data Telemetry

Wireless Power Transfer System With ΣΔ Modulated Transmission Power and Fast Load Response for Implantable Medical Devices

Approximate Matrix Inversion for Linear Pre-coders in Massive MIMO

A Low-Offset Dynamic Comparator with Area-Efficient and Low-Power Offset Cancellation

A Wireless Power Receiver with a 3-Level Reconfigurable Resonant Regulating Rectifier for Mobile-Charging Applications

An Implementation of List Successive Cancellation Decoder with Large List Size for Polar Codes

Approximate Matrix Inversion for Linear Pre-coders in Massive MIMO

BHNN: A Memory-Efficient Accelerator for Compressing Deep Neural Networks with Blocked Hashing Techniques

Concatenated LDPC-Polar Codes Decoding Through Belief Propagation

Dual Transduction Gas Sensor Based on a Surface Acoustic Wave Resonator

A Low-Latency List Successive-Cancellation Decoding Implementation for Polar Codes

A Support Vector Regression (SVR)-based latency model for Network-on-Chip (NoC) architectures

An Implantable Medical Device for Transcorneal Electrical Stimulation: Packaging Structure, Process Flow, and Toxicology Test

BiLink: A High Performance NoC Router Architecture Using bi-Directional Link with Double Data Rate

Performance Evaluation of NoC-Based Multicore Systems: From Traffic Analysis to NoC Latency Modeling

VLSI-SoC: Design for Reliability, Security and Low Power: 23rd IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, Korea, October 5-7, 2015, Revised Selected Papers

A 6.78MHz 6W Wireless Power Receiver with a 3-Level 1x / 1/2 x / 0x Reconfigurable Resonant Regulating Rectifier

A Low-Power Chopper Bandpass Amplifier for Biopotential Sensors

A WLAN 2.4-GHz RF Energy Harvesting System With Reconfigurable Rectifier For Wireless Sensor Network

An Indoor Solar Energy Harvesting System Using Dual Mode SIDO Converter with Fully Digital Time-Based MPPT

Hardware decoders for polar codes: An overview

Low-Complexity List Successive-Cancellation Decoding of Polar Codes Using List Pruning

Low-Latency Approximate Matrix Inversion for High-Throughput Linear Pre-Coders in Massive MIMO

LRADNN: High-throughput and Energy-efficient Deep Neural Network Accelerator Using Low Rank Approximation

Wireless body sensor network system for health monitoring

A 13.56 MHz Wireless Power Transfer System With Reconfigurable Resonant Regulating Rectifier and Wireless Power Control for Implantable Medical Devices

FSNoC: A Flit-level Speedup Scheme for Network On-chips Using Self-reconfigurable Bidirectional Channels

Power Management Analysis of Inductively-Powered Implants with 1X/2X Reconfigurable Rectifier

Reconfigurable Resonant Regulating Rectifier With Primary Equalization for Extended Coupling- and Loading-Range in Bio-Implant Wireless Power Transfer

A Fast Variable Block Size Motion Estimation Algorithm with Refined Search Range for a Two-layer Data Reuse Scheme

Efficient wireless power transmission technology based on above-CMOS integrated (ACI) high quality inductors

Fluxless Packaging of an Implantable Medical Device for Transcorneal Electrical Stimulation

Low complexity belief propagation polar code decoder

Low-latency List Decoding of Polar Codes With Double Thresholding

UHF energy harvesting system using reconfigurable rectifier for wireless sensor network

Wireless Power Transfer System Using Primary Equalizer for Coupling- and Load-Range Extension in Bio-Implant Applications

A Novel Single-Inductor Dual-Input Dual-Output DC-DC Converter With PWM Control for Solar Energy Harvesting System

An Efficient Partial-Sum Network Architecture for Semi-Parallel Polar Codes Decoder Implementation

Cell-type-specific labeling of synapses in vivo through synaptic tagging with recombination

Sequential axon-derived signals couple target survival and layer specificity in the Drosophila visual system

A Thermal Aware Routing Algorithm for Application-Specific Network-on-Chip

A 13.56MHz Wireless Power Transfer System with Reconfigurable Resonant Regulating Rectifier and Wireless Power Control for Implantable Medical Devices

A Comprehensive and Accurate Latency Model for Network-on-Chip Performance Analysis

A fast intermode decision algorithm based on analysis of inter prediction residual

An Adaptive Wireless Powering and Data Telemetry System for Optic Nerve Stimulation

An Efficient Network-on-chip (NoC) Based Multicore Platform for Hierarchical Parallel Genetic Algorithms

Disease Diagnosis-on-a-chip: Large Scale Networks-on-chip Based Multicore Platform for Protein Folding Analysis

Low-latency MAP demapper architecture for coded modulation with iterative decoding

Energy Harvesting and Power Delivery for Implantable Medical Devices

Energy Harvesting and Power Delivery for Implantable Medical Devices

A 13.56MHz fully integrated 1X/2X active rectifier with compensated bias current for inductively powered devices

A Diamond Search Window based Adaptive Search Range Algorithm

Performance Evaluation of Multicore Systems: From Traffic Analysis to Latency Predictions (Embedded tutorial)

VLSI-SoC 2011 – The Advanced Research for Systems-on-chips

A Flit-level Speedup Scheme For Network-on-Chips Using Self-Reconfigurable Bi-directional Channels

A new charge pump analysis and efficiency optimization method for on-chip charge pump

A New Multi-phase power Clocking Architecture for Adiabatic Reversible Energy Recovery Logic

A Novel Offset Cancellation Technique for Dynamic Comparator Latch

A Traffic-aware Adaptive Routing Algorithm on a Highly Reconfigurable Network-on-Chip Architecture

Analysis and design strategy of on-chip charge pumps for micro-power energy harvesting applications

Low-complexity Rotated QAM Demapper for the Iterative Receiver Targeting DVB-T2 Standard

Pipelined architecture of low energy SAR ADC

Rate and Power Allocation for 2-Level Superposition Coded Modulation Supporting Both Unicast and Multicast Traffic

Solar energy harvesting system design using re-configurable charge pump

SVR-NoC: A performance analysis tool for Network-on-Chips using learning-based support vector regression model

Low energy multi-stage level converter for sub-threshold logic

Vibration Energy Scavenging System With Maximum Power Tracking for Micropower Applications

A fault-tolerant network-on-chip design using dynamic reconfiguration of partial-faulty routing resources

A fault-tolerant NoC using combined link sharing and partial fault link utilization scheme

A low-complexity image compression algorithm for Address-Event Representation (AER) PWM image sensors

A Thermal-aware Application Specific Routing Algorithm for Network-on-Chip Design

An adaptive multi-stage rectifier for RF energy harvesting applications

Design and analysis of on-chip charge pumps for micro-power energy harvesting applications

Efficient iterative receiver for LDPC coded wireless IPTV system

Thermal modeling of three-dimensional integrated circuits considering the thermal removal capability of different TSVs

A system-on-chip EPC Gen-2 passive UHF RFID tag with embedded temperature sensor

An Energy Efficient Layered Decoding Architecture for LDPC Decoder

Joint Routing and Sleep Scheduling for Lifetime Maximization of Wireless Sensor Networks

A single inductor DIDO DC-DC converter for solar energy harvesting applications using band-band control

A system-on-chip EPC Gen-2 passive UHF RFID tag with embedded temperature sensor

Analysis of the heat removal capability of the power distribution network in 3D ICs

Maximizing the Harvested Energy for Micro-power Applications through Efficient MPPT and PMU Design

System Level Power Optimizations for EPC RFID Tags to Improve Sensitivity Using Load Power Shaping and Operation Scheduling

Regulated Switched-Capacitor Doubler With Interleaving Control for Continuous Output Regulation

The Design of a Micro Power Management System for Applications Using Photovoltaic Cells With the Maximum Output Power Control

A Hybrid Algorithm and its Re-configurable Architecture for MIMO Detector

A low energy two-step successive approximation algorithm for ADC design

A single inductor dual input dual output DC-DC converter with hybrid supplies for solar energy harvesting applications

An inductor-less MPPT design for light energy harvesting systems

Dual-Power-path RF-DC Multi-Output Power Management Unit for RFID Tags

Improving the hardware utilization efficiency of partially parallel LDPC decoder with scheduling and sub-matrix decomposition

Low Energy Level Converter Design for Sub-V(th) Logics

A single-chip UHF RFID reader in 0.18 mu m CMOS process

IPqML:基于QIP标准的IP质量评测辅助系统

Minimizing the dynamic and sub-threshold leakage power consumption using least leakage vector-assisted technology mapping

Ultra fast fixed-frequency hysteretic buck converter with maximum charging current control and adaptive delay compensation for DVS applications

A low energy two-step successive approximation algorithm for ADC design

A low power layered decoding architecture for LDPC decoder implementation for IEEE 802.11n LDPC codes

A single-chip UHF RFID reader in 0.18-μm CMOS

An energy-adaptive MPPT power management unit for micro-power vibration energy harvesting

An SC voltage regulator with novel area-efficient continuous output regulation by dual-branch interleaving control scheme

An SC voltage regulator with novel area-efficient continuous output regulation by dual-branch interleaving control scheme

Integrated single-inductor dual-input dual-output boost converter for energy harvesting applications

Threshold voltage start-up boost converter for sub-mA applications

A mux-based high-performance single-cycle CMOS comparator

Analysis and Design Strategy of UHF Micro-Power CMOS Rectifiers for Micro-Sensor and RFID Applications

Low-power limited-search parallel state Viterbi decoder implementation based on scarce state transition

A batteryless vibration-based energy harvesting system for ultra low power ubiquitous applications

A Micro Power Management System and Maximum Output Power Control for Solar Energy Harvesting Applications

A mixed-signal architecture of channel select filtering with oversampled ADC for multi-standard RFID reader receiver

A mixed-signal architecture of channel select filtering with oversampled ADC for multi-standard RFID reader receiver

A robust, input voltage adaptive and low energy consumption level converter for sub-threshold logic

A Scalable Frame-Level Pipelined Architecture for FSBM Motion Estimation

An inductor-less micro solar power management system design for energy harvesting applications

An ultra fast fixed frequency buck converter with maximum charging current control and adaptive delay compensation for DVS applications

Design and implementation of a low-power baseband-system for RFID tag

Energy-aware synthesis of networks-on-chip implemented with voltage islands

Low power VLSI design for a RFID passive tag baseband system enhanced with an AES cryptography engine

Low power VLSI design for a RFID passive tag baseband system enhanced with an AES cryptography engine

Single-Chip UHF RFID reader in 0.18- μm CMOS

Vibration Energy Scavenging and Management for Ultra Low Power Applications

High Performance Low Power Completion Detection Circuit

High-performance single clock cycle CMOS comparator

Integrated low-loss CMOS active rectifier for wirelessly powered devices

Modelling of multilayer on-chip transformers

A low power Viterbi decoder implementation using Scarce State Transition and path pruning scheme for high throughput wireless applications

A mixed-signal architecture of channel select filtering with oversampled ADC for multi-standard RFID reader receiver

A novel charge based computation system and control strategy for energy harvesting applications

Adaptively-biased capacitor-less CMOS low dropout regulator with direct current feedback

An integrated 1.8V to 3.3V regulated voltage doubler using active diodes and dual-loop voltage follower for switch-capacitive load

Energy-aware optimal workload allocation among the battery-powered devices to maximize the co-operation life time

High efficiency cross-coupled doubler with no reversion loss

High performance single clock cycle CMOS comparator

Integrated direct output current control switching converter using symmetrically-matched self-biased current sensors

Low complexity SST Viterbi decoder

Optimal link scheduling on improving best-effort and guaranteed services performance in network-on-chip systems

Ultra-low voltage power management circuit and computation methodology for energy harvesting applications

A physical analytical model of multilayer on-chip inductors

A Programmable Integrated Digital Controller for Switching Converters with Dual-band Switching and Complex Pole-zero Compensation

A data discarding framework for reducing the energy consumption of Viterbi decoder in decoding broadcasted wireless multi-resolution JPEG2000 images

A threshold-based algorithm and VLSI architecture of a K-best lattice decoder for MIMO systems

Charge redistribution loss consideration in optimal charge pump design

Exploiting dynamic workload variation in low energy preemptive task scheduling

Gate control strategies for high efficiency charge pumps

Ultra-low voltage power management and computation methodology for energy harvesting applications

An Integrated One-cycle Control Buck Converter with Adaptive Output and Dual Loops for Output Error Correction

Exploiting dynamic workload variation in offline low energy voltage scheduling

A dual-band switching digital controller for a buck converter

Adaptive spectrum-based variable bit truncation of discrete cosine transform (DCT) for energy-efficient wireless multimedia communication

Dynamic reconfigurable bus encoding scheme for reducing the energy consumption of deep sub-micron instruction bus

Fast adaptive DC-DC conversion using dual-loop one-cycle control in standard digital CMOS process

Integrated 0.9V charge-control switching converter with self-biased current sensor

Least leakage vector assisted technology mapping for total power optimization

Minimizing energy consumption of hard real-time systems with simultaneous tasks scheduling and voltage assignment using statistical data

Minimizing Energy Consumption of Multiple-Processors-Core Systems with Simultaneous Tasks Allocation, Scheduling and Voltage Assignment

Power Control of CDMA Systems With Successive Interference Cancellation Using the Knowledge of Battery Power Capacity

Re-configurable bus encoding scheme for reducing power consumption of the cross coupling capacitance for deep sub-micron instruction bus

Scalable scheduling architectures for high-performance crossbar-based switches

A gate duplication technique for timing optimization

A pseudo-CCM/DCM SIMO switching converter with freewheel switching

Single-inductor multiple-output switching converters with time-multiplexing control in discontinuous conduction mode

An integrated digital controller for DC-DC switching converter with dual-band switching

Design and implementation of high-speed arbiter for large scale VOQ crossbar switches

High performance and low power completion detection circuit

Simultaneous task allocation, scheduling and voltage assignment for multiple-processors-core systems using mixed integer nonlinear programming

Single-inductor dual-input dual-output switching converter for integrated battery charging and power regulation

Threshold Channel Estimation for OFDM in Wireless Systems

A 2Gb/s 256{*}256 CMOS crossbar switch fabric core design using pipelined MUX

A Fast Response Adaptive DC-DC Switching Converter using On-chip Dual-Loop One-cycle control

A pseudo-CCM / DCM SIMO switching converter with freewheel switching

A pseudo-CCM/DCM SIMO switching converter with freewheel switching

A VLSI Architecture of a K-Best Lattice Decoding Algorithm for MIMO Channels

Bi-directional integrated charge pumps

CMOS Crossbar S

Low complexity OFDM receiver using Log-FFT for coded OFDM system

Performance study of OFDM receiver using FFT based on Log number system

Stable round-robin scheduling algorithms for high-performance input queued switches

Maximum Likelihood Lattice Decoding for MIMO Channels

Reducing Power Consumption of Turbo-Code Decoder Using Adaptive Iteration with Variable Supply Voltage

A 1.8V single-inductor dual-output switching converter for power reduction techniques

A single-inductor dual-output integrated DC/DC boost converter for variable voltage scheduling

Reduced-Complexity Maximum Likelihood Lattice Decoder for MIMO Channels

Single-inductor multiple-output switching converters with bipolar outputs

Low Power Rake Receiver and Viterbi Decoder Design for CDMA Applications

Low-power VLSI design for motion estimation using adaptive pixel truncation

A low complexity architecture of the V-BLAST system

A low power VLSI architecture of SOVA-based Turbo-code decoder using scarce state transition scheme

A reduced complexity implementation of the Log-Map algorithm for Turbo-codes decoding

Composite interference cancellation scheme for CDMA systems

Low complexity VLSI implementation of a Joint Successive Interference Cancellation with Interleaving scheme

Low power 2-D array VLSI architecture for block matching motion estimation using computation suspension

Low power controller optimization based on data path pattern extraction

VLSI implementation of a switch fabric for mixed ATM and IP traffic

VLSI Implementation of Rake Receiver for IS-95 CDMA Testbed Using FPGA

A/I net: A network that integrates ATM and IP

A real-time sub-carrier allocation scheme for multiple access downlink OFDM transmission

Adaptive tracking of optimal bit and power allocation for OFDM systems in time-varying channels

Adaptive tracking of optimal bit and power allocation for OFDM systems in time-varying channels

Finite state machine partitioning for low power

Low power ACS unit design for the Viterbi Decoder

Reducing Power Consumption of Turbo Code Decoder Using Adaptive Iteration With Variable Supply Voltage

Unequal error protection for wireless transmission of MPEG audio

Accurate and efficient power simulation strategy by compacting the input vector set

Gate-level power estimation using tagged probabilistic simulation

Generic VLSI architecture for block-matching motion estimation algorithms

Low-power state assignment targeting two- and multilevel logic implementations

Rate determination algorithms in IS-95 forward traffic channels

Towards the Capability of Providing Power-area-delay Trade-off at the Register Transfer Level

VLSI design of an ATM switch with automatic fault detection

A Power Estimation Framework for Designing Low Power Portable Video Applications

Efficient and reconfigurable VLSI architecture for different block matching motion estimation algorithms

Exploring the power consumption of different motion estimation architectures for video compression

Low Power Motion Estimation Design Using Adaptive Pixel Truncation

Low power soft output viterbi decoder scheme for Turbo Code decoding

Improving the efficiency of power simulators by input vector compaction

Power estimation methods for sequential logic-circuits

Low power state assignment targeting two- and multi-level logic implementations

Power efficient technology decomposition and mapping under an extended power consumption model

Saving power in the control path of embedded processors

Exact and approximate methods for calculating signal and transition probabilities in FSMs

Exact and Approximate Methods of Switching Activity Estimation in Sequential Logic Circuits

Low Power Architectural Design and Compilation Techniques for High-Performance Processor

Efficient Estimation of Dynamic Power Consumption under a Real Delay Model

Power Estimation Considering Charging and Discharging of Internal Nodes of CMOS Gates

Technology decomposition and mapping targeting low power dissipation

A Full Range Design Automation System for Instruction Set Microprocessor

Application-driven design automation for microprocessor design

A 6.78-MHz Single-Stage Wireless Power Receiver Using a 3-Mode Reconfigurable Resonant Regulating Rectifier

Article

Chopper Capacitively-Coupled Instrumentation Amplifier Capable of Handling Large Electrode Offset for Biopotential Recordings

Article

High-Throughput and Energy-Efficient Belief Propagation Polar Code Decoder

Article

Optic Nerve Stimulation System with Adaptive Wireless Powering and Data Telemetry

Article

Wireless Power Transfer System With ΣΔ Modulated Transmission Power and Fast Load Response for Implantable Medical Devices

Article

Approximate Matrix Inversion for Linear Pre-coders in Massive MIMO

Book chapter

A Low-Offset Dynamic Comparator with Area-Efficient and Low-Power Offset Cancellation

Conference paper

A Wireless Power Receiver with a 3-Level Reconfigurable Resonant Regulating Rectifier for Mobile-Charging Applications

Conference paper

An Implementation of List Successive Cancellation Decoder with Large List Size for Polar Codes

Conference paper

Approximate Matrix Inversion for Linear Pre-coders in Massive MIMO

Conference paper

BHNN: A Memory-Efficient Accelerator for Compressing Deep Neural Networks with Blocked Hashing Techniques

Conference paper

Concatenated LDPC-Polar Codes Decoding Through Belief Propagation

Conference paper

Dual Transduction Gas Sensor Based on a Surface Acoustic Wave Resonator

Conference paper

A Low-Latency List Successive-Cancellation Decoding Implementation for Polar Codes

Article

A Support Vector Regression (SVR)-based latency model for Network-on-Chip (NoC) architectures

Article

An Implantable Medical Device for Transcorneal Electrical Stimulation: Packaging Structure, Process Flow, and Toxicology Test

Article

BiLink: A High Performance NoC Router Architecture Using bi-Directional Link with Double Data Rate

Article

Performance Evaluation of NoC-Based Multicore Systems: From Traffic Analysis to NoC Latency Modeling

Article

VLSI-SoC: Design for Reliability, Security and Low Power: 23rd IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, Korea, October 5-7, 2015, Revised Selected Papers

Book

A 6.78MHz 6W Wireless Power Receiver with a 3-Level 1x / 1/2 x / 0x Reconfigurable Resonant Regulating Rectifier

Conference paper

A Low-Power Chopper Bandpass Amplifier for Biopotential Sensors

Conference paper

A WLAN 2.4-GHz RF Energy Harvesting System With Reconfigurable Rectifier For Wireless Sensor Network

Conference paper

An Indoor Solar Energy Harvesting System Using Dual Mode SIDO Converter with Fully Digital Time-Based MPPT

Conference paper

Hardware decoders for polar codes: An overview

Conference paper

Low-Complexity List Successive-Cancellation Decoding of Polar Codes Using List Pruning

Conference paper

Low-Latency Approximate Matrix Inversion for High-Throughput Linear Pre-Coders in Massive MIMO

Conference paper

LRADNN: High-throughput and Energy-efficient Deep Neural Network Accelerator Using Low Rank Approximation

Conference paper

Wireless body sensor network system for health monitoring

Conference paper

A 13.56 MHz Wireless Power Transfer System With Reconfigurable Resonant Regulating Rectifier and Wireless Power Control for Implantable Medical Devices

Article

FSNoC: A Flit-level Speedup Scheme for Network On-chips Using Self-reconfigurable Bidirectional Channels

Article

Power Management Analysis of Inductively-Powered Implants with 1X/2X Reconfigurable Rectifier

Article

Reconfigurable Resonant Regulating Rectifier With Primary Equalization for Extended Coupling- and Loading-Range in Bio-Implant Wireless Power Transfer

Article

A Fast Variable Block Size Motion Estimation Algorithm with Refined Search Range for a Two-layer Data Reuse Scheme

Conference paper

Efficient wireless power transmission technology based on above-CMOS integrated (ACI) high quality inductors

Conference paper

Fluxless Packaging of an Implantable Medical Device for Transcorneal Electrical Stimulation

Conference paper

Low complexity belief propagation polar code decoder

Conference paper

Low-latency List Decoding of Polar Codes With Double Thresholding

Conference paper

UHF energy harvesting system using reconfigurable rectifier for wireless sensor network

Conference paper

Wireless Power Transfer System Using Primary Equalizer for Coupling- and Load-Range Extension in Bio-Implant Applications

Conference paper

A Novel Single-Inductor Dual-Input Dual-Output DC-DC Converter With PWM Control for Solar Energy Harvesting System

Article

An Efficient Partial-Sum Network Architecture for Semi-Parallel Polar Codes Decoder Implementation

Article

Cell-type-specific labeling of synapses in vivo through synaptic tagging with recombination

Article

Sequential axon-derived signals couple target survival and layer specificity in the Drosophila visual system

Article

A Thermal Aware Routing Algorithm for Application-Specific Network-on-Chip

Book chapter

A 13.56MHz Wireless Power Transfer System with Reconfigurable Resonant Regulating Rectifier and Wireless Power Control for Implantable Medical Devices

Conference paper

A Comprehensive and Accurate Latency Model for Network-on-Chip Performance Analysis

Conference paper

A fast intermode decision algorithm based on analysis of inter prediction residual

Conference paper

An Adaptive Wireless Powering and Data Telemetry System for Optic Nerve Stimulation

Conference paper

An Efficient Network-on-chip (NoC) Based Multicore Platform for Hierarchical Parallel Genetic Algorithms

Conference paper

Disease Diagnosis-on-a-chip: Large Scale Networks-on-chip Based Multicore Platform for Protein Folding Analysis

Conference paper

Low-latency MAP demapper architecture for coded modulation with iterative decoding

Conference paper

Energy Harvesting and Power Delivery for Implantable Medical Devices

Article

Energy Harvesting and Power Delivery for Implantable Medical Devices

Book chapter

A 13.56MHz fully integrated 1X/2X active rectifier with compensated bias current for inductively powered devices

Conference paper

A Diamond Search Window based Adaptive Search Range Algorithm

Conference paper

Performance Evaluation of Multicore Systems: From Traffic Analysis to Latency Predictions (Embedded tutorial)

Conference paper

VLSI-SoC 2011 – The Advanced Research for Systems-on-chips

Book

A Flit-level Speedup Scheme For Network-on-Chips Using Self-Reconfigurable Bi-directional Channels

Conference paper

A new charge pump analysis and efficiency optimization method for on-chip charge pump

Conference paper

A New Multi-phase power Clocking Architecture for Adiabatic Reversible Energy Recovery Logic

Conference paper

A Novel Offset Cancellation Technique for Dynamic Comparator Latch

Conference paper

A Traffic-aware Adaptive Routing Algorithm on a Highly Reconfigurable Network-on-Chip Architecture

Conference paper

Analysis and design strategy of on-chip charge pumps for micro-power energy harvesting applications

Conference paper

Low-complexity Rotated QAM Demapper for the Iterative Receiver Targeting DVB-T2 Standard

Conference paper

Pipelined architecture of low energy SAR ADC

Conference paper

Rate and Power Allocation for 2-Level Superposition Coded Modulation Supporting Both Unicast and Multicast Traffic

Conference paper

Solar energy harvesting system design using re-configurable charge pump

Conference paper

SVR-NoC: A performance analysis tool for Network-on-Chips using learning-based support vector regression model

Conference paper

Low energy multi-stage level converter for sub-threshold logic

Article

Vibration Energy Scavenging System With Maximum Power Tracking for Micropower Applications

Article

A fault-tolerant network-on-chip design using dynamic reconfiguration of partial-faulty routing resources

Conference paper

A fault-tolerant NoC using combined link sharing and partial fault link utilization scheme

Conference paper

A low-complexity image compression algorithm for Address-Event Representation (AER) PWM image sensors

Conference paper

A Thermal-aware Application Specific Routing Algorithm for Network-on-Chip Design

Conference paper

An adaptive multi-stage rectifier for RF energy harvesting applications

Conference paper

Design and analysis of on-chip charge pumps for micro-power energy harvesting applications

Conference paper

Efficient iterative receiver for LDPC coded wireless IPTV system

Conference paper

Thermal modeling of three-dimensional integrated circuits considering the thermal removal capability of different TSVs

Conference paper

A system-on-chip EPC Gen-2 passive UHF RFID tag with embedded temperature sensor

Article

An Energy Efficient Layered Decoding Architecture for LDPC Decoder

Article

Joint Routing and Sleep Scheduling for Lifetime Maximization of Wireless Sensor Networks

Article

A single inductor DIDO DC-DC converter for solar energy harvesting applications using band-band control

Conference paper

A system-on-chip EPC Gen-2 passive UHF RFID tag with embedded temperature sensor

Conference paper

Analysis of the heat removal capability of the power distribution network in 3D ICs

Conference paper

Maximizing the Harvested Energy for Micro-power Applications through Efficient MPPT and PMU Design

Conference paper

System Level Power Optimizations for EPC RFID Tags to Improve Sensitivity Using Load Power Shaping and Operation Scheduling

Conference paper

Regulated Switched-Capacitor Doubler With Interleaving Control for Continuous Output Regulation

Article

The Design of a Micro Power Management System for Applications Using Photovoltaic Cells With the Maximum Output Power Control

Article

A Hybrid Algorithm and its Re-configurable Architecture for MIMO Detector

Conference paper

A low energy two-step successive approximation algorithm for ADC design

Conference paper

A single inductor dual input dual output DC-DC converter with hybrid supplies for solar energy harvesting applications

Conference paper

An inductor-less MPPT design for light energy harvesting systems

Conference paper

Dual-Power-path RF-DC Multi-Output Power Management Unit for RFID Tags

Conference paper

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A mixed-signal architecture of channel select filtering with oversampled ADC for multi-standard RFID reader receiver

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Low power VLSI design for a RFID passive tag baseband system enhanced with an AES cryptography engine

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A mixed-signal architecture of channel select filtering with oversampled ADC for multi-standard RFID reader receiver

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